Senior Staff Digital Verification Engineer – Wireline PHYs

Marvell Technology • Toronto, ON

12d • $118,700 - $158,300

About The Position

As a Design Verification Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. Central Engineering provides IP to be used by all the other spokes on that wheel, including Data Center, Storage, Security, and Networking. You’ll be focusing on verification of wireline PHY IP for high-performance SoCs and ASICs. You will be responsible for developing comprehensive verification environments, test plans, and test suites to ensure the functionality, performance, and compliance of PHY designs with industry standards.

Requirements

• BS/MS degree +7 years or PhD +4 years in Electrical Engineering, Computer Engineering, or related fields.
• Strong experience with UVM and SystemVerilog for verification environment development.
• Hands-on experience with Verilog, SystemVerilog, and UVM for creating test benches, test plans, and verification environments.
• Experience with constrained random verification and coverage-driven verification methodologies.
• Familiarity with digital verification in Analog/Mixed-Signal (AMS) designs, preferably in the area of high-speed PHYs for wireline communications (e.g. SerDes, D2D, DDR).
• Some knowledge of the usage of analog behavioral models in the verification of AMS designs.
• Proficiency in scripting languages (Python, Perl, TCL) for test automation and verification infrastructure.
• Experience with protocol checkers, VIPs (Verification IPs), and industry-standard verification tools.
• Proven debugging skills and experience with waveform analysis and coverage analysis tools.

Nice To Haves

• Experience in the use of formal verification and/or assertion-based verification (ABV) would be useful
• understanding of firmware-hardware interaction and system bring-up tools.

Responsibilities

• Develop verification environments in UVM for IP blocks targeting SerDes and Parallel Optics applications.
• Define verification test plans with architecture and design teams, covering all requirements and corner cases.
• Collaborate with analog teams to understand and implement verification requirements for AMS simulations.
• Develop directed and constrained random functional verification tests to achieve comprehensive coverage of PHY functionality.
• Create checkers and scoreboards to verify correct operation across multiple speeds and data formats.
• Implement coverage models and drive verification to reach coverage targets, including code coverage, functional coverage, and assertion coverage.
• Debug test failures using waveform analysis tools and work with designers to resolve issues.
• Develop verification infrastructure including monitors, and drivers for various interfaces (APB, AHB, AXI).
• Write Python, Perl, or TCL scripts to automate verification tasks, improve efficiency, and analyze results.
• Collaborate with firmware teams to verify firmware-hardware interactions and microcontroller integration.
• Mentor junior verification engineers and contribute to improving verification methodologies and best practices.
• Maintain regression test suites and analyze verification metrics to ensure quality and tape-out readiness.

Benefits

• competitive compensation
• great benefits
• workstyle within an environment of shared collaboration, transparency, and inclusivity
• tools and resources they need to succeed in doing work that matters
• grow and develop with us

What This Job Offers

• Job Type: Full-time
• Career Level: Senior