Senior Staff CPU Backend Design Engineer

Qualcomm•Santa Clara, CA

1d•$216,091 - $298,100

About The Position

This individual leads the team to improve engineering efficiency, product quality and responsibility of working with microarchitecture and RTL design team to implement the designs, meeting aggressive power, area and performance goals using industry standard tools/flows. Works with CPU microarchitecture team to understand specifications and design trade-offs in pipeline and structure sizing. Performs feasibilities to validate implementability, area, timing and power. Synthesizes the Verilog RTL into gate level designs and performs optimizations. Performs SynthPlace & Route on the designs using industry standard tools and delivers GDS. Optimizes the design at various stages from RTL to GDS to meet timing, power and area goals. Validates the designs for functional and electrical robustness. Performs Formal Verification & Conformal Low Power checks to meet design functionality requirements, multi voltage domain checks. Implements large complex designs with complete physical integration and stringent timing budgets to meet higher frequencies. Proficient in Calibre DRC/LVS/ERC checks to meet advanced technology physical verification checks qualifying for better manufacturability and yield. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.

Requirements

Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
Nine (9) years of progressive experience in a related occupation.
Proficiency in Calibre DRC/LVS/ERC checks.

Responsibilities

Improve engineering efficiency and product quality.
Work with microarchitecture and RTL design teams to implement designs meeting power, area, and performance goals.
Understand specifications and design trade-offs in pipeline and structure sizing.
Perform feasibility studies to validate implementability, area, timing, and power.
Synthesize Verilog RTL into gate-level designs and perform optimizations.
Perform SynthPlace & Route using industry-standard tools and deliver GDS.
Optimize designs from RTL to GDS to meet timing, power, and area goals.
Validate designs for functional and electrical robustness.
Perform Formal Verification & Conformal Low Power checks.
Implement large, complex designs with complete physical integration and stringent timing budgets.
Perform Calibre DRC/LVS/ERC checks for physical verification.
Act as a strong contributor at design reviews and project meetings.
Communicate and implement a development plan.