Copy of Senior Staff Analog Engineer

Renesas Electronics•Chandler, TX

17h

About The Position

Renesas is seeking a Senior Staff Analog Engineer to lead the architectural evolution of its PMIC and mixed-signal product lines. The role covers the full development lifecycle, from early customer collaboration and specification through design, simulation, silicon verification, and production readiness. The engineer will serve as a technical authority, advise on architectures, mentor engineers, and drive engineering excellence and methodology improvements. The position also contributes to product roadmaps and works with multicultural teams in an innovation-focused environment.

Requirements

At least 8 to 10 years of experience in power management.
A proven record of acting as a technical project lead on complex ICs within the last four years.
A degree-level qualification in Electronics Engineering or a related discipline.
In-depth knowledge of CMOS power management circuits, organizational business objectives, and current market trends.
Demonstrated ability to drive engineering initiatives and process improvements while delivering high-quality results under tight schedule pressure.
Exceptional communication and presentation skills, including the ability to convey complex technical concepts to multicultural teams and external customers.
Ability to work independently as a technical lead while fostering a collaborative environment as a role model and mentor.
High cross-cultural sensitivity and flexibility to undertake occasional international travel at short notice.

Responsibilities

Lead the full development lifecycle of major analog and mixed-signal blocks and top-level PMIC products, from initial specification through design, simulation, and silicon verification.
Serve as a global technical authority and primary point of contact, provide architectural recommendations, and mentor engineers.
Collaborate directly with customers to define system requirements and develop solutions that meet performance, area, and power constraints.
Oversee high-level verification planning, DFT strategy, and lab evaluation in partnership with applications and test engineering teams to prepare designs for production.
Identify and implement company-wide improvements in engineering methodologies, policies, and strategic initiatives.
Support roadmap planning and align technical advice with external market trends and evolving CMOS process technologies.