Senior Software Engineer — RISC-V Instruction Set Simulator (Simulator Engineer)

Qualcomm•Cupertino, CA

5d•$167,100 - $250,700

About The Position

We are building a high-performance, production-grade RISC-V Instruction Set Simulator (ISS) that serves as the golden reference model for a family of next-generation 64-bit RISC-V processors. The ISS is a key component of our verification flow: it drives co-simulation against RTL, powers random test generation, and gives software teams a fast, accurate platform to develop and debug pre-silicon firmware. The work is at the intersection of computer architecture, systems software, and verification engineering — writing the kind of C++ that has to be both correct to the bit and fast enough to run long-running benchmarks and boot Linux.

Requirements

Solid C++ skills and comfort reading unfamiliar codebases.
Comfortable with basic processor architecture, including pipelines, memory, privilege levels, and interrupts.
Strong attention to detail; this work is spec-driven and correctness matters.
Willingness to read a specification document and turn it into tested code.
Some exposure to low-level or systems programming, such as embedded systems, operating systems, compilers, or hardware description.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Nice To Haves

Experience with RISC-V, x86, or ARM architecture.
Familiarity with simulators or emulators such as QEMU, Spike, gem5, or similar tools.
Experience with GDB, ELF binaries, or bare-metal bring-up.
Background in hardware verification or RTL co-simulation.
Knowledge of Linux internals.
Python 3+ experience.

Responsibilities

Implementing the ISA: Translate RISC-V specification chapters into working C++ code. We cover a wide range of extensions: integer, floating-point, vector, bit manipulation, security features, interrupt handling, and more.
Simulation correctness: Help maintain the fetch/decode/execute engine, memory protection, virtual memory, and privilege-level logic that make the simulator a trustworthy reference.
Co-simulation: Work on the harness that runs the ISS alongside RTL and flags any differences, one instruction at a time.
Testing: Write targeted unit tests that exercise individual features and compare against expected results derived from the RISC-V spec.
Developer tooling: Contribute to and maintain a large collection of simulator extensions and utilities that help the user community be more productive.