RISC-V Processor Validation & Test Generation Engineer

Tenstorrent Unlisted/Referral Jobs•Santa Clara, CA
•$100,000 - $500,000•Remote

About The Position

Tenstorrent is seeking an engineer to develop tools and test programs that validate processor behavior and improve compliance with RISC-V specifications, including the RVA23 profile. The role involves building, refining, and verifying automated test-generation tools that exercise processor functionality, uncover bugs, and identify ambiguities or misunderstandings in architectural specifications. A key focus is adapting existing test-generation programs to generate supervisor-mode code instead of machine-mode code, so tests exercise RISC-V cores in ways relevant to real operating systems. The engineer will work across processor architecture, software development, and hardware validation to create portable, effective tests. The position is remote and based in the United States. Candidates at various experience levels are welcome; level and offer will be determined during the interview process.

Requirements

  • Strong knowledge of RISC-V ISA fundamentals, including instruction behavior differences in machine, supervisor, and user modes.
  • Knowledge of the structure of two-stage RISC-V page tables and the ability to generate them.
  • Experience writing low-level software, processor tests, validation programs, or test-generation tools using C/C++, assembly, Python, or similar languages.
  • Ability to read and interpret processor architecture specifications and translate them into reliable, executable test cases.
  • Strong debugging and code-analysis skills.
  • Ability to work independently on a focused technical project, investigate unfamiliar code, and deliver maintainable, well-documented solutions.

Responsibilities

  • Develop, refine, and verify tools and test programs for validating processor behavior and RISC-V architectural compliance, including the RVA23 profile.
  • Adapt existing test-generation programs to replace machine-mode code generation with supervisor-mode code generation.
  • Modify code-generation programs to produce supervisor-mode code that creates page tables and schedules tests.
  • Generate portable tests that exercise processor functionality, uncover bugs, and identify ambiguities or misunderstandings in architectural specifications.
  • Translate processor architecture requirements into executable test cases.
  • Investigate existing code and deliver maintainable, well-documented solutions.
  • Work independently and collaborate with hardware architects and software engineers.
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