Senior SoC Compute/Memory Subsystem Architect
About The Position
The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. We are seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms. This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.
Requirements
- Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.
- 7 + years of experience in the following: SoC / CPU / memory subsystem architecture
- CPU architecture and cache hierarchies
- Memory subsystems (DDR/HBM, controllers, QoS)
- Coherent/Non-Coherent interconnect architectures
- Experience in system-level performance and PPA tradeoff analysis
- Drive architecture definition from concept to silicon
Nice To Haves
- Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
- ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures.
- Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments
- Familiarity with PCIe, CXL, and memory semantics for high performance IO.
- Track record of multi generation architectural ownership and mentoring other architects.
Responsibilities
- Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs
- Architect compute subsystem roles (control plane, data plane assist, offload execution, management services)
- Drive compute architecture decisions balancing performance, power, and area
- Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache)
- Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions)
- Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity
- Architect system memory subsystems including: DDR / LPDDR interfaces, Memory controllers and scheduling policies, Bandwidth provisioning and scaling strategies
- Work with Performance architect in define memory access models for compute, network, and accelerator subsystems
- Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads
- Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads
- Architect features such as: Multi-tenant isolation and security boundaries, Shared vs isolated memory models
- Ensure efficient interaction between host, IPU/DPU compute, and offload engines
- Architect integration between: Compute subsystem, Network subsystem (packet processing pipelines), Storage and accelerator subsystems
- Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead.
- Drive system architecture decisions for balanced SoC performance.
- Define compute and memory strategies for power efficiency and DVFS scalability.
- Architect mechanisms for: Memory bandwidth throttling / prioritization, Per-subsystem scaling
- Optimize performance-per-watt at system level.
- Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations
- Define scaling strategies for: Core count and frequency, Memory bandwidth and capacity, Cache scaling and topology
- Ensure backward compatibility and smooth migration across product lines
- Collaborate with teams across: Networking subsystem (NSS), SoC fabric/interconnect, Firmware, OS, and drivers, Validation and performance modeling and testing
- Drive architecture alignment and resolve cross-domain tradeoff
Benefits
- competitive pay
- stock bonuses
- benefit programs which include health, retirement, and vacation
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Associate degree
