Senior SoC Architect

Intel Corporation•Santa Clara, CA

1d•$170,500 - $315,490•Hybrid

About The Position

We are looking for a strong architecture lead to define and drive architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems. This role combines architecture definition with implementation awareness and performance ownership. The candidate will also work on platform-level performance, including building performance environments and driving closure in partnership with system architects and cross-functional teams. We are looking for someone who can thoughtfully translate system goals into practical, scalable, implementation-ready architecture, while balancing key considerations such as performance, power, area, and schedule. This person brings deep technical expertise and naturally fosters alignment across teams, creating a collaborative environment where ideas can thrive. Through a clear and strategic approach, they help deliver architecture that supports first-time-right integration and enables faster performance closure, ultimately contributing to more efficient and successful outcomes for the team. The architecture must be power-optimized, highly scalable, and practical for implementation across multiple product generations.

Requirements

Bachelor´s degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 6 or more years of relevant technical experience. OR MS degree in a specialized field such as Computer Science, Electrical Engineering, or related discipline along with 4 or more years of relevant technical experience.
Experience in SoC IP architecture for high bandwidth interconnect and/or subsystem design.
Experience writing high-quality architecture specifications used by design and verification teams.
Hands-on experience with power optimization techniques.
Experience defining architecture requirements, interface contracts, performance targets, and power/performance/area trade-offs.
1+ years of experience working with AMBA protocols, especially AXI, CHI, and APB.
1+ years of experience collaborating across architecture and implementation teams.

Nice To Haves

Working with AI tools to develop machine readable specification documents for Spec2Silicon fast and reliable execution.
Deep understanding of coherency concepts and CHI architecture.
Proven expertise in arbitration and routing algorithms, end-to-end QoS (Quality of Service), and high-bandwidth low latency, scalable designs.
Experience with fabric-based scalable platforms across multiple markets or generations.
Exposure to performance modelling, simulation, and data-driven architecture tuning.
In-depth understanding of cache architecture and memory management/address translation MMU, IOMMU.
Familiarity with security architecture and access control frameworks in SoC platforms.
DVFS and Distributed power management.
Background in debug, safety, and RAS architecture.

Responsibilities

Author architecture specifications for Unified Intel Chassis IP components and subsystem integration.
Ensure architecture is implementation-aware, scalable, and power-optimized.
Drive platform performance analysis and closure, including bottleneck identification and optimization.
Build and enhance platform performance environments, models, and benchmarking flows.
Define and validate end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic.
Partner with system architects, RTL/design, verification, firmware/software, and performance teams to align architecture with product goals.
Define architecture trade-offs, assumptions, interfaces, and measurable success criteria.
Support debuggability, safety, reliability, and serviceability requirements in architecture definition.