Senior SoC Chiplet Architect

Intel•Fort Collins, CA

4d•Hybrid

About The Position

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. We are seeking a Senior SoC Chiplet Architect to define and lead the architecture strategy for multi-generation, chiplet-based SoC platforms targeting next-generation data center workloads. This role is responsible for chiplet partitioning, die-to-die (D2D) interconnect architecture, and system-level tradeoff analysis across performance, power, area (PPA), cost/yield, and software complexity. You will drive modular, scalable SoC design approaches, including cross-chiplet coherency, system infrastructure (boot/reset/telemetry), and RAS/security architectures across multi-die systems.

Requirements

Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.
7 + years of experience in the following: SoC/system architecture, including end-to-end architecture definition from requirements to silicon execution
Experience with multi-die / chiplet partitioning and the associated system implications (D2D, boot/reset, cross-domain QoS, debug)
Run architecture trade-off studies and communicate decisions crisply to senior technical and business stakeholders

Nice To Haves

Familiarity with industry direction on chiplet interoperability and standardization and/or participation in ecosystem discussions
Hands-on experience with system bring-up flows and architecture-driven debug/telemetry planning across complex SoCs
Architecture fundamentals in interconnects/fabrics, memory subsystem behavior, performance modeling, and PPA tradeoffs
Experience building or consuming cost/yield models for architectural decision-making (including explicitly scoping what cost elements are included)

Responsibilities

Define the monolithic vs. chiplet decision framework and multi-generation roadmap, incorporating reticle scaling limits, yield economics, modularity, and portfolio reuse strategy
Lead architecture studies for 2-die / 3-die / multi-chiplet scaling (compute + I/O/network + memory/accelerators), including partition boundaries, SKU scalability, and future-proof modular upgrades
Produce executive-ready architecture options and recommendations for leadership decisions (build/partner/standardize)
Drive functional partitioning across chiplets (compute, networking/I/O, accelerators, memory controllers, security/management), balancing PPA, D2D bandwidth/latency, validation complexity, and product flexibility
Define scalable system resource models (e.g., memory channels, PCIe lanes, pipeline scaling) and how these scale with chiplet count and topology
Specify any required logic / gaskets and integration constraints to enable modular assembly and consistent SW-visible behavior
Architect D2D communication for high bandwidth, low latency, and reliability across chiplets; define link budgets and requirements for bandwidth, latency, error handling, and flow control
Define inter-chiplet QoS mechanisms (e.g., arbitration, prioritization, isolation) and ensure the architecture supports workload-driven traffic patterns at scale
Align D2D choices with industry standardization direction (where applicable) and ensure project-specific needs can be encapsulated cleanly
Define coordinated power delivery and power management flows across chiplets (telemetry, quiescence, package states, throttling), including system-level sequencing and corner cases
Architect clocking and reset distribution (reference clock delivery, local PLL strategies, reset sequencing, debug/manufacturing hooks) and ensure robust bring-up across all dies
Drive the chiplet-aware boot and early firmware architecture (e.g., parallel boot considerations, coordinated reset control) in partnership with FW/platform teams
Define cross-chiplet error reporting, containment, and recovery policies, including consistent crashdump, telemetry access, and actionable observability for post-silicon debug
Specify debug/trace infrastructure assumptions to ensure chiplet partitioning does not compromise lab efficiency or field diagnosability
Lead quantitative trade studies across performance, power, area, cost/yield, and schedule; identify bottlenecks and propose architecture-level mitigations
Partner with packaging/manufacturing stakeholders for trade-off comparisons (e.g., explicitly tracking whether packaging overheads are included in a given analysis)
Drive alignment across architecture, RTL, DV, FW/SW, packaging, and platform teams; lead reviews, challenge assumptions, and converge on clear architectural decisions
Work with other architects and contribute reusable patterns/checklists for chiplet-based SoC infrastructure