Senior SoC Architect (f/m/d)

Black Semiconductor

About The Position

We are seeking a skilled Senior SoC Architect at Black Semiconductor to drive the architecture of our entire Electronics-Photonics IC (EPIC) SoC, translating the Marketing Requirement Document (MRD) into a complete, internally consistent, and implementable Product Requirement Document (PRD) covering digital, analog, I/O, and memory subsystems. You will own the digital and high-speed I/O subsystem architecture directly, with particular depth in high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet. Working closely with the Analog/RF System Architect, Photonics System Architect, Package Electrical/SI Architect, memory subsystem owner, product management, and engineering teams, you will integrate their subsystem architectures into one coherent overall product architecture.

Requirements

7–10 years of experience in SoC or product architecture roles, with proven SoC/product architecture ownership and demonstrated experience taking a product from MRD-level requirements through a complete, implementable PRD-level architecture covering multiple subsystems and at least one full product architecture cycle.
Deep, hands-on high-speed I/O subsystem expertise, particularly high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol requirements shape physical-layer architecture.
Strong digital subsystem and interconnect fabric architecture experience, including defining on-chip interconnect and digital subsystem partitioning for a complex SoC.
Strong cross-domain integration skills, with the ability to take analog, photonic, packaging, and memory architecture input from peer subsystem owners and integrate it into one internally consistent PRD without needing to personally own those domains.
Experience translating marketing/product-level requirements into precise, engineering-actionable architecture specifications and reasoning about full-chip performance, power, and area (PPA) trade-offs.
Experience with 3rd-party IP vendors, including evaluating and selecting external IPs and design integration partners.
Experience with architecture specification and requirements management tooling for authoring and maintaining the PRD and tracing it back to the MRD; UCIe, PCIe, and Ethernet protocol/standards documentation and compliance tooling; architecture and performance modeling tools, including custom or commercial full-chip performance/power models; Python / C++ for modeling, scripting, and analysis; and collaboration and documentation platforms for coordinating input from analog, photonics, packaging, memory, and other subsystem architects into a single PRD.

Nice To Haves

Previous experience serving as an SoC Chief Engineer, with end-to-end accountability for a product's full-chip architecture, schedule, and quality outcomes.
Familiarity with silicon photonics or electro-optic I/O, and how it changes traditional I/O subsystem architecture assumptions.
Familiarity with advanced packaging, including 2.5D/3D and chiplet integration, and its impact on full-chip architecture choices.
Experience working directly with product management and/or customers to shape MRD-level requirements.
Experience with CXL or other die-to-die/coherent interconnect standards adjacent to UCIe/PCIe.

Responsibilities

Own the overall EPIC SoC technical leadership from initial concept through production and drive cross-functional technical alignment across photonics, analog, digital, technology, and product teams.
Build and document the overall product architecture, translating the MRD into a complete PRD and ensuring architectural decisions, technical requirements, dependencies, and trade-offs are consistently aligned across teams.
Own the digital subsystem architecture, including core logic, on-chip interconnect fabric, and subsystem partitioning.
Own the high-speed I/O subsystem architecture, with particular depth in high-speed SerDes and the protocol digital logic for UCIe, PCIe, and Ethernet, including how protocol layers map onto the physical SerDes implementation.
Partner with the Analog/RF System Architect, Photonics System Architect, Package Electrical/SI Architect, and memory subsystem owner to integrate their architectures and ensure the full-chip architecture is internally consistent and feasible within the target electrical, physical, and packaging constraints.
Drive full-chip performance, power, and area (PPA) trade-off analysis, partner with external vendors/3rd-party IP providers on full-chip validation and characterization teams on product characterization, and make the calls needed to keep the PRD internally consistent.
Present the integrated architecture and PRD to product management and engineering leadership and own it through to sign-off.