Senior Silicon Design Engineer

Microsoft•Redmond, WA

1d•$119,800 - $261,000

About The Position

Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering organization powers its cloud infrastructure and online services. Within it, the Compute Silicon & Manufacturing Engineering organization designs, develops, manufactures, and packages Microsoft computer chips, including Azure Cobalt. The Shared and Custom IP & Silicon team supports hardware manufacturing and cloud hardware planning, quality, delivery, scale, and sustainability. Microsoft is seeking a Senior Silicon Design Engineer to develop leading-edge custom IP as part of the SCIPS team. The role involves owning IP RTL development from microarchitecture through implementation, verification, and post-silicon validation; developing high-performance, power-efficient designs; and collaborating across architecture, SoC, firmware, verification, and physical design. The engineer will lead design signoff and timing closure, contribute hardware algorithms for data-processing acceleration, debug silicon and system issues, and mentor engineers while improving design practices.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of experience; or a bachelor's degree in one of these fields and at least 5 years of experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Provide proof of citizenship, U.S. residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship will be verified with a valid passport, with other documents accepted for lawful permanent residents, refugees, and asylees where applicable.

Nice To Haves

At least 3 years of experience in digital logic design using SystemVerilog, Verilog, or VHDL.
At least 3 years of experience running synthesis and static-check tools, including RTL synthesis, lint, CDC, RDC, and/or LEC.
Proficient expertise in digital design, microarchitecture specification development, and synthesizable RTL implementation.
Ability to read and write code in Python, Perl, C/C++, C#, or a related language.
Experience developing and optimizing high-speed CMOS designs, including power, performance, and area tradeoff analysis.
Proficient debugging, problem-solving, and cross-functional collaboration skills throughout the IP development lifecycle.
Proficient knowledge of industry-standard interconnect protocols, including AMBA AXI.
Experience with synthesis, floorplanning, static timing analysis, timing closure, and collaboration with physical design teams.
Proficient written and verbal communication skills, with the ability to work independently and collaborate effectively across teams.

Responsibilities

Own development of custom IP RTL from microarchitecture through RTL implementation, verification, and post-silicon validation.
Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high-quality IP solutions.
Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle.
Lead design signoff activities, including CDC, RDC, LINT, synthesis, STA, and timing closure.
Design leading-edge hardware algorithms to accelerate key data-processing operations.
Drive pre-silicon and post-silicon debug, silicon bring-up, and root-cause analysis of complex system issues.
Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements.