MTS Silicon Design Engineer

Advanced Micro Devices, Inc•Santa Clara, CA

About The Position

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: AMD’s Network Technologies Solutions Group (NTSG) develops advanced networking silicon and software for data center, cloud, and enterprise infrastructure. We are seeking a hands-on MTS Design Verification Engineer to lead verification of complex networking IP, subsystems, and SoCs. You will define verification strategy, develop scalable environments, influence architecture and microarchitecture, and drive functional and performance verification to signoff. You will work on next-generation technologies spanning high-speed Ethernet, PCIe, DMA, packet processing, traffic management, virtualization, and hardware-software interactions. THE PERSON: We are seeking a high‑impact MTS Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high‑performance ASIC designs. The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels. You will work in a fast‑paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking products.

Requirements

Expert‑level knowledge of SystemVerilog and UVM
Strong hands‑on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained‑random methodologies
Strong debug skills across architecture, RTL, and testbench layers
Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data‑path components
Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure

Nice To Haves

Packet-processing pipelines, switch fabrics, schedulers, packet buffers, or traffic managers.
Experience with performance verification, power‑aware verification (UPF), or formal verification
Familiarity with FPGA/HAPS‑based validation and acceleration flows
Exposure to architectural modeling or C/C++ reference models
Strong analytical and problem‑solving abilities with a proven track record of debugging complex issues
Ability to lead verification tasks independently and drive cross‑team closure
Excellent verbal and written communication skills
Comfortable working in a fast‑paced, collaborative, multi‑site environment
Ability to mentor and guide junior DV engineers

Responsibilities

Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC‑level verification.
Drive test plan creation, feature mapping, and coverage strategy for complex networking and data‑path IP.
Develop high‑quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.
Verify networking and data‑path functions including Ethernet, PCIe, DMA, packet processing, switch fabrics, and traffic management.
Develop scenarios covering packet forwarding, buffering, ordering, arbitration, flow control, error handling, and recovery.
Verify throughput, latency, bandwidth, fairness, QoS, congestion, and other performance requirements using realistic traffic and stress workloads.
Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
Root‑cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
Optimize simulations, coverage closure, and verification sign‑off methodology.
Use industry‑standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).
Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high‑quality deliverables.
Participate in design reviews, micro‑architecture definition, and bring a verification perspective into early design stages.
Mentor junior engineers and provide technical leadership within the verification team.