Senior Silicon ATE Development Test Engineer, Amazon Leo Silicon Team

AmazonSan Diego, CA
$159,200 - $247,600Onsite

About The Position

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As Senior Silicon ATE Development Test Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions. You will work closely with an internal inter-disciplinary team, and third party suppliers to drive key aspects of product definition, execution and optimization. You must be responsive, flexible and able to succeed within an open collaborative peer environment. You’ll be responsible for development and engineering of high-volume production test methodology for custom SoCs for Leo. You’ll be part of the team that creates a chip and system test infrastructure and methodology applicable to transmit and receive communication systems. Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Requirements

  • Bachelor's degree in Electrical/Communications Engineering, or experience working in electrical engineering field
  • 5+ years of experience in RF Test or RF Product Engineering, preferably in high-volume consumer devices manufacturing.
  • Strong written and verbal skills.
  • International travel required during release to production phases.

Nice To Haves

  • Experience with digital / SERDES tests such as scan, MBIST, Vmin search, and loopback.
  • Experience with JTAG and boundary-scan techniques.
  • Understand of and experience with DFT and DFM.
  • Experience with wafer sort and final test ATE hardware development, and debugging.
  • Experience with running firmware on DUTs to reduce test time and increase self-testability.
  • Knowledge of PCB design requirements and layout best practices for high-speed signaling.
  • Excellent understanding of wireless electronic manufacturing, assembly and especially test processes in advanced nodes such as 4nm and below.
  • Knowledgeable in production control processes, statistical analysis platforms (Galaxy, Spotfire, JMP or similar), data interpretation/analysis, Cp/Cpk, and bench/tester correlation.
  • Working knowledge of scripting languages such as Python, PERL, and Tcl/Tk

Responsibilities

  • Write test plans and test programs for SoCs tested on Teradyne and Advantest equipment.
  • Develop and review load board, socket, and probe card designs and simulation results for best layout practices and possible signal / power integrity issues.
  • Convert test patterns from the DFT team into tester-suitable formats (e.g. ATP).
  • Run test vectors on test platforms and optimize tester and vector parameters to ensure timing and repeatability.
  • Work with ASIC design teams ensure the test equipment and processes required for production meet Amazon standards for high-volume manufacturing.
  • Optimize equalization settings for up to 224 Gbps SERDES running on ATE platforms.
  • Actively identify test related readiness, issues, and optimizations throughout the product lifecycle and work towards expedient resolutions.
  • Assist in qualification activities such as burn-in board design, HTOL, ESD, etc.

Benefits

  • health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
  • 401(k) matching
  • paid time off
  • parental leave
  • sign-on payments
  • restricted stock units (RSUs)
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