Senior SI/PI Engineer - AI and Compute Server Design

Hyve Solutions•Fremont, CA

21h

About The Position

Hyve Solutions transforms complex engineering challenges into production reality for technology innovators building AI, cloud, and connected infrastructure. As a US-based manufacturing partner, the company rapidly delivers fast, agile execution through deep technical partnerships and co-innovation, and supply chain clarity. Hyve’s integrated ODM, CM, and SI capabilities eliminate vendor complexity while accelerating time-to-market with single-partner accountability from design through scale. The company co-innovates with deep engineering expertise, treating customer success as its own while building tomorrow's digital infrastructure. At Hyve Solutions, signal and power integrity are among the most critical disciplines in delivering reliable, high-bandwidth AI and compute servers. As next-generation platforms push PCIe Gen5/Gen6, CXL, NVLink, DDR5/DDR6, and 224G SerDes to their limits, disciplined SI/PI engineering is essential to first-pass success. This role focuses on hands-on signal-integrity and power-integrity analysis, simulation, and lab correlation for Hyve's next-generation AI and compute server platforms.

Requirements

Bachelor's or Master's in Electrical Engineering or a related field.
6+ years of hands-on SI/PI experience for servers, GPU platforms, or high-speed digital systems, with proven delivery of designs into production.
Strong knowledge of high-speed channel design, PDN design and analysis, connector/cable modeling, and PCB stackup/materials; proficiency with SI/PI simulation tools (e.g., HFSS, ADS, HSPICE, Sigrity) and high-speed lab measurement equipment.
Familiarity with PCIe, CXL, DDR JEDEC, and Ethernet electrical specifications and compliance methodologies.
Able to translate analysis into clear, actionable design guidance and collaborate effectively across board, layout, and mechanical teams.

Responsibilities

Perform pre- and post-layout SI analysis for high-speed interfaces including PCIe Gen5/Gen6, CXL, NVLink, Ethernet/SerDes, and DDR5/DDR6 memory, defining channel budgets, routing rules, and equalization strategies.
Design and validate power delivery networks, including PDN impedance targeting, decoupling strategy, and IR-drop analysis for high-current GPU, CPU, and VR rails.
Build and run models using tools such as HFSS, ADS, HSPICE, Sigrity, or equivalent; develop IBIS-AMI and S-parameter-based channel simulations.
Execute measurements with high-speed oscilloscopes, VNAs, TDRs, and BER testers; correlate simulation to lab data and drive corrective design changes.
Partner with board designers, layout, and mechanical teams to embed SI/PI rules into stackups, routing, and connector/cable selection, and support EVT/DVT/PVT bring-up and debug.