Senior Scale-Up Network System Architect

NVIDIA•Santa Clara, CA

2d•$184,000 - $356,500

About The Position

NVIDIA seeks a Senior Scale-Up Network System Architect to develop the next generation of NVLink-based scale-up networking for leading AI supercomputing platforms. You will develop the complete architecture of the interconnect that links GPUs within and between racks. This fabric enables sizable AI training and inference clusters to function as a single large accelerator. This system-level role involves teamwork across silicon, firmware, software, and topology development. You will translate workload and customer needs into architectural choices that will be part of NVIDIA’s flagship AI systems for years.

Requirements

Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.
8+ years of industry experience in computer networking, system architecture, or high-performance interconnects.
Strong grasp of network structure and dynamics at scale, including the impact of topology, congestion, and failure modes on distributed workload performance.
Experience developing or using simulation/modeling environments to evaluate architecture trade-offs.
Strong multi-functional collaboration skills — comfortable driving alignment across hardware, firmware, and software teams without direct authority over them.
Clear technical communication, including the ability to explain complex architecture trade-offs to both engineering and non-engineering collaborators.

Nice To Haves

Direct experience with NVLink, NVSwitch, or comparable scale-up interconnect technologies.
Hands-on experience with high-performance networking transports such as RoCE (RDMA over Converged Ethernet), including concepts low-latency transport, congestion control, and lossless fabric build.
Experience with memory subsystem architecture, including memory hierarchies, cache coherency, and memory technologies such as HBM, DDR, or LPDDR.
Working knowledge of large-scale AI model architectures and how they map to network requirements.
Background in HPC or supercomputing-scale interconnect development.

Responsibilities

Define end-to-end system architecture for next-generation NVLink scale-up networks, from link and switch behavior through rack- and pod-level topology.
Convert AI training and inference workload needs (LLM, MoE, and emerging model architectures) into specific networking, bandwidth, latency, and resiliency specifications.
Drive architecture trade-off studies across performance, cost, power, and reliability, and build the models needed to justify those decisions with data.
Collaborate closely with ASIC, firmware, software, and systems teams to ensure architecture decisions are implementable and land accurately in silicon and product.
Develop and use simulation and analytical models to validate architecture choices before committing to silicon.
Represent system architecture in multi-functional and customer-facing technical discussions, and serve as a technical expert on scale-up network behavior at scale.