Senior Research Engineer, AI Assisted Chip Design, DeepMind

Google•Mountain View, CA

8d•$174,000 - $252,000

About The Position

As a Senior Research Engineer on Google DeepMind’s AI-assisted chip design team, you will develop and apply state-of-the-art AI methods—including multi-turn agentic flows, reinforcement learning (RLVR, RLAIF, RLHF), and evolutionary search—to chip design. You will collaborate closely with research and production silicon teams across Google, working with hardware architects, RTL/DV engineers, and ML model developers to integrate research into production chips. You will use Gemini to optimize the electronic design automation (EDA) life cycle and accelerate silicon development. The work spans complex design stages, improving Gemini for silicon applications to streamline hardware design and verification, enhance efficiency, and reduce time to market. The team includes research scientists, research engineers, and software engineers, and has delivered research breakthroughs with impact on real products and flagship Google silicon. Google DeepMind is an interdisciplinary AI lab focused on advancing AI to address complex global challenges and support product innovation. It emphasizes widespread public benefit, scientific discovery, and safety and ethics. Individual pay is determined by job-related skills, experience, and relevant education or training. The listed US compensation is $174,000–$252,000, plus a 15% bonus target, equity, and benefits.

Requirements

Bachelor’s degree or equivalent practical experience.
5 years of experience with software development in one or more programming languages.
3 years of experience building and shipping technical products, including experience in Generative AI and Large Language Models (LLM).
3 years of experience testing, maintaining, or launching software products.
1 year of experience with software design and architecture.

Nice To Haves

Master’s degree or PhD in Computer Science or a related technical field.
1 year of experience in a technical leadership role.
Experience developing accessible technologies.

Responsibilities

Architect, build, and scale multi-turn agentic flows with Gemini and evolutionary workflows (e.g., AlphaEvolve) to improve chip design.
Develop and curate LLM benchmarks for chip design to evaluate and advance frontier model capabilities.
Use scalable evaluation and reinforcement learning post-training workflows to improve Gemini models for chip design.
Build on AI-for-silicon breakthroughs, including AI-driven RTL and logic optimization methods that have delivered power, performance, and area improvements on flagship production chips, and help shape the chip design industry.
Use AI to automate complex chip-design tasks, including spec-to-RTL generation, RTL optimization, RTL debugging, and automated Design Verification (DV).