Senior QPU Design Engineer

IonQ•College Park, MD

34d

About The Position

We are looking for a Senior QPU Design Engineer to join our Processor Design team at Oxford Ionics, now part of IonQ. You will be responsible for integrating all the features required to operate our quantum computers into complex chips, contributing to the team's mission of advancing the design of high performance quantum processing units. You will work closely with scientists and fabrication engineers to bring new designs for ion trapping chips into production, and you will play an important part in shaping the hardware behind our work building the world's most advanced quantum systems.

Requirements

Experience translating design requirements into features.
Hands-on experience in chip layout.
Ability to work across teams to discuss the many aspects of chip design.
Understanding how different parts of a chip influence and constrain one another.
Ability to take on layout work themselves.
Effective contribution within a fast moving and highly technical team.
Ability to drive the design process.
Ability to solve problems as they arise.
Responsibility for delivery.
Experience guiding chips through the full design process, from requirements through to layout and tape-out.
Experience laying out complex, multi-layer chips, including metal-track routing and interfaces with photonics and CMOS.
Collaborate with scientists to understand their requirements and agree specifications.
Coordinate with other teams to ensure feasibility and compatibility.
Comfortable taking charge of projects independently and owning the delivery of the final tape-out.

Nice To Haves

Experience in scripted generation of layout, using GDSFactory in Python or similar.
Experience using Cadence for IC layout.
Experience in ion trap design, photonics design or IC packaging.

Responsibilities

Turn operational requirements into chip layout, supporting the delivery of devices that enable new technologies.
Expand the range of features our chips support, contributing directly to the goal of building utility scale quantum computers.
Guiding chips through the design process, from requirements to layout and tape out.
Laying out complex multi layer chips, including metal track routing and interfaces with photonics and CMOS.
Collaborating with scientists to discuss their requirements and settle on specifications.
Coordinating with other teams to ensure feasibility and compatibility.
Taking charge of projects independently and owning delivery of the final tape out.