Senior Design Engineer

Micron•San Jose, CA

About The Position

As a Senior Design Engineer in Micron Technology’s NVE Design Engineering Core group, you will contribute to developing best-in-class memory products by applying specialized knowledge and Micron proprietary methods to design and analyze core and mixed-signal circuits. The role focuses on NAND circuit design, analysis, optimization, and validation, while supporting power reduction and manufacturability. It also involves developing Python-based AI utilities that work with EDA tools to accelerate development workflows, along with reviewing documentation and generating build collateral. The engineer collaborates with cross-functional teams to optimize product manufacturability, cost, reliability, and time to market. The US base salary range is $120,000–$252,000 per year. Additional compensation may include benefits, bonuses, and equity. Pay within the stated range depends on work location and job-related factors such as knowledge, skills, experience, tenure, and education or training. Micron offers medical, dental, and vision plans, income-protection programs, paid family leave, paid time off, and paid holidays. Micron is an equal opportunity and affirmative action employer.

Requirements

Bachelor’s degree in electrical engineering is required.
At least 2 years of proven NAND-design-relevant experience is required.
High level of self-motivation.
Proficiency in analog/mixed-signal circuit design, including charge pumps, op amps, DACs, ADCs, linear regulators, oscillators, and bandgaps.
Strong fundamentals in semiconductor and device physics and analog/mixed-signal circuit design.
Understanding of semiconductor reliability issues, including CHC, NBTI, stress, and snapback, as well as electromigration (EM) and IR analysis.
Strong circuit-debugging and problem-solving skills.
Experience in circuit verification and optimization, circuit layout planning, parasitic extraction, and guiding layout.
Ability to employ AI tools, such as Claude.
Excellent teamwork attitude.
Good verbal communication skills in English and ability to convey sophisticated technical concepts verbally and in writing.

Nice To Haves

Master’s or Ph.D. degree, or equivalent experience.
Knowledge of analog and digital simulators such as HSPICE, Fast SPICE, and Verilog.
Familiarity with Cadence design and LVS/DRC tools.
Experience with a scripting language.
Familiarity with Linux/UNIX.

Responsibilities

Design, simulate, optimize, and floor-plan NAND circuit blocks.
Evaluate design feasibility and analyze circuit functionality across use cases.
Implement analog and mixed-signal circuit designs that meet performance and reliability specifications.
Validate design performance at block and chip level using industry-standard simulation tools.
Collaborate with multifunctional teams to analyze and reduce NAND power consumption.
Build and maintain Python-based AI utilities that collaborate with EDA tools to accelerate development workflows, such as environment setup, corner execution, regressions, automated documentation, and predictive build/layout.
Review existing user documentation and generate new build collateral.
Collaborate with Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to optimize manufacturability, cost, reliability, and time to market.