Senior Product Manager, Hardware (NPU IP)

quadric • Burlingame, CA

6d • $200,000 - $250,000 • Hybrid

About The Position

Quadric is seeking a Senior Product Manager, Hardware to own the roadmap for their innovative General-Purpose Neural Processing Unit (GPNPU) architecture, the Chimera GPNPU. This role involves defining feature sets for upcoming IP generations, driving architecture freeze decisions, and collaborating with global SoC customer teams to ensure their silicon IP powers production devices. The ideal candidate will have a strong background in hardware product management, NPU/AI accelerators, SoC integration, or semiconductor IP licensing, and experience leading technical architecture reviews with sophisticated buyers.

Requirements

• 5–8 years of Product Management experience focused on hardware or silicon products, with a senior IC background.
• Direct experience in at least two of the following: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, or semiconductor IP licensing.
• Proven experience leading technical architecture reviews with sophisticated buyers (Tier-1 automotive, OEM SoC teams).
• Active adoption of agentic AI tools (e.g., Claude Code, Cursor, or equivalent) in daily workflows.
• EE/CE/CS engineering degree (or equivalent depth).
• Based in or willing to relocate to the Bay Area (Burlingame hybrid model).
• Willing to travel quarterly (domestic and international).

Nice To Haves

• Prior RTL or silicon-implementation background (e.g., shipped a block, went through tape-out, or owned a microarchitecture spec).
• Experience working at a semiconductor IP vendor (e.g., Synopsys, Arm, Ceva, Cadence, Imagination, VeriSilicon).
• Direct exposure to AI/ML compute stack architectures (dataflow, quantization, sparsity, mixed-precision trade-offs).
• Experience engaging with Japanese-market customers and technical teams.

Responsibilities

• Own the Chimera GPNPU IP roadmap across five strategic tracks: Compute, Efficiency, Scalability, Safety, and Integration.
• Set feature sets for upcoming IP generations and drive architecture freeze decisions.
• Partner directly with anchor SoC customer teams worldwide to ensure silicon IP powers production devices.
• Translate customer requirements, competitive pressures, and architectural constraints into track-by-track feature lists with explicit gating.
• Build the business and technical case for contested architecture decisions and lead trade-off reviews with architects.
• Drive IP usability by identifying silent customer workarounds and productizing proper architectural solutions.
• Serve as the named hardware product owner for key anchor accounts, presenting new features and integrating formal architecture feedback into the product roadmap.
• Conduct architecture reviews with technical buyers, including Tier-1 automotive and OEM SoC design teams.
• Partner with international customers, particularly supporting key anchor accounts in the Japanese and global semiconductor markets.
• Analyze competitive architectures to anticipate market needs and inform product requirements.
• Define and position SoC integration features, specifying which knobs are exposed and productized.
• Sequence functional safety positioning, lockstep configurations, FMEDA work, and safety-island architectures for automotive and critical application standards.

Benefits

• Medical, dental, and vision insurance from day one - Premiums covered at 99% for Employees
• Company-paid life Insurance
• Voluntary supplemental life insurance
• STD + LTD insurance
• Commuter support including parking or Caltrain reimbursement
• FSA + HSA
• Equity with the business
• Paid Parental Leave
• 401(k) Retirement Plan
• Flexible PTO
• Winter holiday shutdown
• Catered lunch each day in our office
• Collaborative, low-ego culture with significant ownership and impact
• A work culture focused on innovative disruption

What This Job Offers

• Job Type: Full-time
• Career Level: Senior