Senior/Principal Physical Verification Engineer
Celero Communications•San Jose, CA
•Remote
About The Position
We are seeking a Senior to Principal Full-Chip Physical Verification Engineer to lead our physical verification efforts. This role involves owning execution plans, schedules, and ensuring the quality and tapeout readiness of our chips. You will conduct full chip and block-level PV checks, collaborate with internal teams, and provide guidance on verification strategies.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or related field
- 7+ years of experience with full-chip verifications
- Proven hands-on experience with Physical Verification tool (ICV/Calibre)
- Able to assemble a flow to support block/chip level PV
- Strong expertise in Floorplanning to avoid DRC/LVS issues
- Provide guidance to analog IP team to allow for clean integration
Nice To Haves
- Experience in advanced technology nodes (7nm, 5nm, 3nm)
- Automation skills using Tcl, Python, or shell scripting
Responsibilities
- Lead full chip Physical Verification effort
- Own execution plans, schedules for full-chip
- Drive accountability for quality, milestones, and tapeout readiness
- Conduct full chip and blocks PV checks
- Ownership of full chip verification
- Work with internal analog team to ensure clean IP delivery
- Responsible for running and analyzing DRC/ERC/LUP/PERC results
- Partner with analog, block, chip top owners to ensure clean floorplan
- Provide early guidance on corner case requirements
- Influence floorplan constraints, hierarchy, and implementation strategy
- Participate in tapeout readiness reviews
Benefits
- Annual Base Salary Range: $150,000 - $250,000
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What This Job Offers
Job Type
Full-time
Career Level
Senior
