Senior/Principal Physical Design Engineer

Celero Communications • Irvine, CA

4d • Remote

About The Position

We are seeking a Senior to Principal Physical Design Engineer to join our team. This role involves the complete physical implementation of System-on-Chips (SoCs) or complex digital blocks, from RTL to GDSII. You will be responsible for managing key aspects of chip design, including floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to achieve optimal chip performance. A significant part of the role includes resolving timing, congestion, and EM/IR issues in collaboration with Frontend Designers, as well as performing signoff and verification tasks such as Static Timing Analysis (STA) and physical verification. You will also be responsible for fixing Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations. Additionally, this position requires driving automation and improving flow robustness through scripting languages and leading cross-functional collaboration with architects, logic designers, and analog design teams to ensure tapeout readiness.

Requirements

• 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
• Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
• Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Responsibilities

• Own physical implementation of System-on-Chips (SoCs) or complex digital blocks from RTL to GDSII.
• Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Resolve timing, congestion, and EM/IR issues together with Frontend Designers.
• Run Static Timing Analysis (STA) and physical verification.
• Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Partner with architects, logic designers, and analog design teams for tapeout readiness.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed