Senior Principal Engineer, Design Verification

Marvell Technology•Westborough, MA

2d•$204,900 - $303,250

About The Position

Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology. Analyze designs and architectures to develop test strategies that will ensure functional correctness. Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete. Debug failures and work with designers to resolve issues. Contribute and drive the development and future direction of SoC verification methodologies and environments. Independently proposes and defines new high-level technical work. Provide leadership for a geographically dispersed team of verification professionals in pre-silicon validation of a highly complex SoC design.

Requirements

Bachelor’s degree in Electrical engineering, Electronics, Computer engineering, or related fields with 15+ years of experience.
Master’s degree and/or PhD in Electrical engineering, Electronics, Computer engineering, or related fields with 10+ years of experience.
PhD in Electrical engineering, Electronics, Computer engineering, or related fields with 8+ years of experience.
Strong experience in architecture and implementation of complex/random verification testbench environments using System Verilog/UVM.
10+ years of direct hands-on verification experience at block, subsystem and full chip level contexts.
Technical leadership experience in driving SoC teams with multi domain technical expertise for validating SoCs.
Strong experience with developing and executing detailed verification test-plans with coverage.
Extensive experience with scripting languages such as Python or Perl and EDA verification tools, as well as bug tracking and regression mechanisms.
Expertise in cross functional collaboration for driving outcomes and to participate in problem-solving and quality improvement activities.
Expertise in guiding and mentoring technical teams for successful execution.
Ability to generate ideas, take up initiatives and drive the verification productivity gains.
Must have the ability to define problems, issues, and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
Must have the ability to multi-task in a fast-paced environment.

Responsibilities

Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers using System Verilog and UVM methodology.
Analyze designs and architectures to develop test strategies that will ensure functional correctness.
Develop verification testplan and write tests using random techniques and coverage analysis, and work with designers to ensure it is complete.
Debug failures and work with designers to resolve issues.
Contribute and drive the development and future direction of SoC verification methodologies and environments.
Independently proposes and defines new high-level technical work.
Provide leadership for a geographically dispersed team of verification professionals in pre-silicon validation of a highly complex SoC design.