As a SoC-level design verification engineer, you will be responsible for the development and maintenance of UVM testbench components and other verification testing collaterals. You will be expected to provide a level of leadership in a team charged with ensuring design quality in a variety of complex SoC architectures. Analyze architectures and designs to create comprehensive test plans and strategies. Organize and lead the development of verification environments and methodologies. Develop tests/testing strategies to achieve coverage goals. Debug failures and work with designers to resolve issues. Help mentor junior engineers in growing their knowledge and skills.
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Job Type
Full-time
Career Level
Principal