Principal Engineer, Design Verification Engineering

Analog Devices•Austin, TX

3d•$197,600 - $250,920•Hybrid

About The Position

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X. Come join ADI – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare. ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering or closely related technical discipline (willing to accept foreign education equivalent) and ten (10) years of experience as a Design Verification Engineer or related occupation performing pre-silicon design verification.
Demonstrated Expertise (“DE”) developing test benches using System Verilog and OVM or UVM including test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, and assertion-based verification techniques.
DE in Verilog, C or C++, revision control systems such as Perforce or Git, EDA tools and scripting (Python, Perl or Shell) used to build infrastructure, tools, and flows for verification environments.
DE architecting and implementing Design Verification infrastructure and executing the full verification cycle.
DE with pre- and post-silicon verification test flow and automated test benches.
DE with verification of ARM or RISC-V based sub-systems or SoCs.

Responsibilities

Verification of digital designs and sub-systems using leading edge verification methodologies.
Contribute and influence the decisions on methodologies to be adopted for the verification.
Architect the testbench and develop the test infrastructure in System Verilog and UVM.
Integrate the block level testbench in chip-level UVM environment and verify integration.
Define test plans, tests and verification methodology for block / chip level verification.
Work with the design team in generating test-plans and closure of code and functional coverage.
Continuous interaction with design teams in enabling top-level chip verification.
Support post silicon verification activities of the products working with design, product evaluation, and applications engineering team.