Senior Principal Engineer, Chip Lead, Photonic Fabric Chiplet

Marvell Technology•Santa Clara, CA

4d•$182,360 - $273,200

About The Position

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. The Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions. The Photonic Fabric™ includes optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies. This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or related fields and 15+ years of related professional experience OR Master’s degree / PhD in Computer Science, Electrical Engineering or related fields with 8-12 years of experience.
15+ years of experience in ASIC / SoC development with end‑to‑end chip ownership.
Strong experience across Micro‑architecture and RTL design, high‑speed analog SERDES, physical design and sign‑off, DFT and manufacturing test, advanced packaging and chiplet‑style integration, post‑silicon bring‑up, ATE, and system validation.
Ability to clearly articulate architectural and implementation tradeoffs across performance, power, area, yield, cost, schedule, and risk.
Strong track record of driving alignment across cross‑functional teams with differing viewpoints in a matrixed environment and drive solutions to tough engineering problems across the product stack.
Excellent written and verbal communication skills, including leading technical reviews and communicating status, risks, and decisions to engineering and product leadership at the executive level.
While deep expertise across all domains is not expected, the ideal candidate will demonstrate the maturity and technical judgment to foster a culture of cross-domain collaboration and deal with conflicts in a calm and constructive fashion.

Nice To Haves

Prior experience in delivery of high‑speed I/O and/or optical products into production.
Prior experience as Chip Lead, SoC Architect, or System‑Level Technical Lead.

Responsibilities

Own the end‑to‑end product design spanning Electrical IC, Photonic IC, firmware stack, and advanced packaging design.
Lead micro‑architecture and RTL development for the Electrical IC that can include high speed SERDES and digital subsystems with internally developed IPs and industry standard external IPs such as UALink, UCIe, etc.
Collaborate with verification team to ensure robust functional and performance verification spanning digital RTL, AMS and electrical-optical interfaces.
Work closely with physical design and packaging teams on floorplanning, physical implementation, timing, power, and physical verification closure.
Partner with DFT experts to drive DFT strategy for digital, analog SERDES, and system‑level testability.
Partner with photonics team to define PIC architecture, interfaces, and control schemes, and ensure robust electrical-optical co‑design.
Collaborate with test engineering to drive ATE enablement, test program development, and debug.
Lead cross-functional team to complete system‑level validation, including boards, optics, firmware, and software interaction.
Drive root‑cause analysis across silicon, package, optics, and system domains.
Mentor and develop senior engineers and influence cross functional teams across disciplines in a matrixed environment.
Identify and communicate technical status, risks, and tradeoffs to engineering and product leadership.