Photonic Design Automation Engineer

PsiQuantum • Palo Alto, CA

2d

About The Position

PsiQuantum is building the first useful quantum computers using a silicon photonic architecture. This role is for a Photonic Netlist & Design Automation Engineer who will own and scale the layout-to-netlist and multi-physics integration flow for our silicon photonics platform. The position involves working at the intersection of photonic circuit design, CAD infrastructure, and electromagnetic (EM) modeling. The engineer will be responsible for ensuring schematic, layout, and extracted models remain consistent, automatable, and simulation-ready. This role is the technical owner of netlist generation, extraction, verification, and automation pipelines, enabling reliable photonic IC tape-outs.

Requirements

• Bachelors or other advanced degrees in Computer Science or related engineering fields.
• MS or PhD in Electrical Engineering, Applied Physics, or related field.
• 6+ years experience in: Photonic IC design, Analog/mixed-signal CAD/EDA, Custom IC flow automation.
• Strong Python scripting skills.
• Experience with layout tool (KLayout, Cadence Virtuoso, etc.).
• Experience with EM solver (Lumerical FDTD/MODE, HFSS, CST, Tidy3D).
• Experience with Circuit simulator (SPICE, INTERCONNECT, Caphe, PhotonForge).
• Excellent verbal and written communication skills with an ability to communicate effectively to a variety of audiences.
• Strong critical thinking, creative, innovative, analytical, and detail-oriented problem-solving skills.
• Proven track record of impactful results.
• Ability to work independently with limited direction.
• Demonstrated ability to lead and juggle multiple priorities and deliver against a schedule.
• Demonstrated interest in quantum computing.
• Ability to contribute to a fast-paced start-up environment.

Responsibilities

• Define and maintain the photonic netlist methodology.
• Develop and maintain photonic and electronic LVS flows.
• Generate simulation-ready netlists for circuit/system tools.
• Interface with other teams to deliver PIC netlist artifacts that fit into an overall system design.
• Ensure accurate extraction of parasitics (optical, electrical, thermal).
• Build CI/CD automation pipelines connecting: Layout tools, EM solvers, Circuit simulators.
• Develop Python automation for extraction and model generation.
• Implement regression testing for netlist consistency.
• Improve reproducibility of design-to-simulation workflows.
• Collaborate with PDK engineers to maintain model libraries.

Benefits

• Equity
• Benefits

What This Job Offers

• Job Type: Full-time
• Career Level: Senior