Senior Power Integrity Co-Design Engineer

NVIDIA•Santa Clara, CA

6d•$136,000 - $264,500•Hybrid

About The Position

The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment.

Requirements

BS / MS / PhD in EE, CE, or related (or equivalent experience).
5+ years in silicon power integrity, voltage noise, or PDN.
Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, voltage regulator response.
Hands-on silicon experience: bringup, characterization, correlation.
Comfortable on a bench with scopes, probes, DAQ — and in front of a simulator.
Strong Sim-to-Si correlation instincts — the field of figuring out which side of the equals sign is wrong.
System-level objectivity.
Willingness to make the call that's right for the product even when no single component team agrees with you.
Multi-functional collaboration in a matrixed environment.
Ability to drive a decision through five collaborators without burning bridges, and write it down when done.
Spec rigor. Live in spec lock, sign-off, and OPP closure — the work isn't done until it's documented and shipped.

Nice To Haves

Patents or publications in power integrity, voltage noise, PDN, or di/dt mitigation.
Hands-on with groundbreaking GPU, CPU, or AI accelerator silicon — Hopper / Blackwell / Rubin-class or hyperscaler equivalents.
ML/AI applied to noise modeling, transient prediction, droop response, or feature optimization.
Multi-rail, multi-domain PDN ownership at SoC level — die + package + board co-optimization in production.
Track record of codifying methodology into reusable workflows or tooling.

Responsibilities

Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them.
Co-design noise features with Speed, Power, Reliability, Circuit Design, Power-Arch, ASIC, and platform teams.
Define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
Build and take ownership of the Sim-to-Si correlation methodology for noise.
Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them.
Lead show-stopper noise bugs during bringup.
Drive architecture-level codesign tradeoffs across V/F <-> Power <-> Noise <-> Reliability <-> Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives.