Senior Physical Verification CAD Engineer

Microsoft • Raleigh, NC

4d

About The Position

Do you have a passion for advanced silicon signoff and physical verification at leading-edge technology nodes? You will be part of a team responsible for driving state-of-the-art Physical Verification CAD solutions for Microsoft’s silicon design teams. In this role, you will foster the enablement and support of advanced-node DRC, LVS, Antenna, and ESD signoff flows, working closely with EDA vendors, and internal design teams. You will own PV signoff methodology end to end, identify gaps, and drive scalable, production-ready solutions across multiple silicon programs. We are committed to a diverse and inclusive workspace and strongly encourage applicants from all backgrounds and walks of life. Difference makes us better.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
• OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
• OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
• OR equivalent experience.
• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Nice To Haves

• Experience with industry-standard PV tools, such as Calibre.
• Scripting skills in at least one language (TCL, Python, Perl, or equivalent) for flow automation, debug, and data analysis.
• Ability to debug complex, cross-domain issues, reason about root cause (design vs flow vs tool), and drive issues to closure across teams.
• BS + 12 years / MS + 10 years of relevant experience.
• SVRF rule or deck development experience, including customization, enablement, or debug support.
• Experience with advanced verification checks, such as: o PERC (including custom or CNOD-based checks) o ESD, EOS, level-shifter, and reliability-focused verification. ·
• Exposure to shift-left PV methodologies, TCIC flows, and early-stage verification strategies that improve convergence and reduce late-stage surprises.
• Prior experience contributing to or leading PV, methodology councils, or multi-project enablement efforts.

Responsibilities

• Develop, maintain, and support Physical Verification (PV) flows across all Silicon projects, spanning early design (shift-left) through final signoff, including DRC, LVS, ERC, antenna, and advanced checks.
• Own PV methodology, including guidelines, checklists, milestone definitions, and waiver strategies, ensuring consistent and predictable execution across programs and nodes.
• Partner closely with Physical Design teams to: Enable early PV runs o Debug complex DRC/LVS/ERC/PERC issues o Identify systemic design or flow gaps and drive fixes to closure.
• Lead resolution of PV-related flow and design issues, including tool stability, runtime scalability, deck integration, waiver correctness, and cross-tool debug.
• Drive cross-functional alignment with CAD, Technology, and external EDA partners (e.g.,Siemens, Synopsys) to communicate PV requirements, influence roadmap priorities, and unblock execution at critical project milestones.
• Support PDK and node enablement activities, ensuring PV flows are validated, production-ready, and aligned with foundry decks and internal signoff criteria across multiple technology variants.
• Contribute to PV activities, including training material, documentation, onboarding labs, and continuous improvement of automation and debug infrastructure.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: Ph.D. or professional degree