Senior CAD Engineer

Saige Partners•San Jose, CA

5d•Onsite

About The Position

We are seeking a highly skilled Senior CAD Engineer to support advanced semiconductor design and verification environments across leading-edge technology nodes. This role will be responsible for PDK enablement, CAD flow development, and layout validation, with a strong focus on ensuring robust, scalable, and high-quality design infrastructure for successful tapeouts. The ideal candidate brings deep expertise in CAD tools, semiconductor processes, and physical verification, along with a strong problem-solving mindset and the ability to collaborate across design and engineering teams.

Requirements

Master’s degree in Electrical Engineering, Physics, or a related field (equivalent combination of education and relevant industry experience will be considered)
Minimum 7+ years of experience in CAD engineering with direct involvement in advanced node tapeouts
Strong experience with parasitic extraction and verification tools, such as: Cadence Quantus / QuantusFS, Calibre xRC / xACT / xACT3D
Hands-on knowledge of Calibre LVS and DRC flows and rule decks
Experience with 3D field solvers, such as: Cadence EMX, Ansys HFSS
Solid understanding of: Semiconductor technology and fabrication processes, Semiconductor device physics, Process modeling and mask layout concepts
Familiarity with BEOL and FEOL process architectures, including: Planar, FD-SOI, FinFET, Gate-All-Around (GAA)
Strong analytical and problem-solving skills with exceptional attention to detail
Excellent written and verbal communication skills with the ability to work effectively in team environments
Self-motivated with a continuous improvement and growth mindset

Nice To Haves

Proven track record of supporting multiple technology nodes and complex tapeouts
Experience enhancing CAD flows through automation and scripting

Responsibilities

Perform PDK installation, configuration, and validation for advanced technology nodes (e.g., 4nm, 2nm and beyond)
Develop, implement, and maintain CAD flows and design environments, including: Cadence Virtuoso, Calibre DRC/LVS, Cadence EMX and Quantus
Support top-level layout and sub-cell development, ensuring design integrity and compliance
Interpret, analyze, and debug layout and verification issues across multiple design stages
Execute and optimize parasitic extraction and physical verification flows
Collaborate with cross-functional teams (design, layout, verification) to improve flow efficiency and quality of results (QoR)
Ensure readiness and reliability of CAD infrastructure for advanced node tapeouts
Develop automation, checks, and methodologies to improve design productivity and accuracy