Senior Photonic Layout Design Engineer

NVIDIA•Santa Clara, CA

8d•$132,000 - $235,750

About The Position

Are you seeking an outstanding opportunity? We are looking for a Senior Photonic Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal & Silicon Photonic Designs! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Join our diverse team today!

Requirements

Deep technical understanding of advanced node semiconductor fabrication, sophisticated automation capabilities, and a proven track record of first-time success on high-density chip designs.
BS, MS, or Ph.D. in Electrical Engineering, Physics, or a closely related field (or equivalent experience).
At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries.
Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics within advanced sub-micron CMOS and SiPh technologies.
Proven expertise with Cadence Virtuoso (Custom Layout, SDL) and industry-standard verification suites (Calibre, Hercules, ICV, Dracula, or Primeyield).
Strong proficiency in programming and scripting languages (Python, SKILL, Perl, TCL, or C++) for layout automation, file I/O, data processing, and tape-out flows.
Ability to optimize workflows using best-known methods (BKMs), and proactively collaborate with integration, and design rule teams to achieve high-yield manufacturing goals.

Responsibilities

Lead complex, full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal functions (high-speed/general I/Os, ESD structures).
Drive the full tape-out process, including floor planning, waveguide routing, and mask data preparation.
Execute rigorous post-layout verification (DRC, LVS, fill, density) across multiple stepping versions.
Trace defect sources, mitigate layout-dependent issues, and ensure DRC/LVS cleanliness prior to tape-out.
Own the layout of complex test structures, active/passive full loops, and certification vehicles with large Design of Experiments (DOEs) to optimize for process windows.
Develop and implement AI-assisted design methods, layout automation scripts, and custom Pcells to improve productivity, reduce development cycle times, and customize DRC/LVS checking flows.