Package Design & Layout Engineer

Cspeed • Palo Alto, CA

1d • Onsite

About The Position

Cspeed IO is a stealth startup backed by Sutter Hill Ventures and Atreides Capital, headquartered in Palo Alto, CA. Our executive team has a proven track record of building and scaling category-defining semiconductor and infrastructure businesses at leading companies. Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, aiming to replace traditional copper interconnects with advanced fiber-optic technologies that overcome current limitations. This role offers a unique opportunity to own the physical design of our optical engine packages, including redistribution layers, substrates, and the bump and ball maps connecting the die stack to the host board. It is a hands-on layout position with significant architectural influence, requiring close collaboration with PIC and EIC design teams, SI/PI and thermal engineers, and supply chain partners.

Requirements

• BS or MS in Electrical Engineering, or equivalent practical background.
• 6+ years of IC package physical design experience, with at least one product taken from concept through tape-out and volume-relevant build.
• Expert-level proficiency in a package layout tool: Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC Package, or equivalent.
• Demonstrated experience with multi-die packaging: 2D or 2.5/3D integration.
• Working fluency with multi-layer organic substrate construction and understanding how material and stack-up choices constrain routing.
• Practical experience closing DFM/DFA with external substrate suppliers and OSATs.
• Comfortable working in English across a distributed team and multiple time zones.

Nice To Haves

• Demonstrated experience with advanced packaging: 2.5D/3D integration, RDL, TSV interposers, fan-out, microbump or Cu-pillar flip-chip.
• Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power integrity workflows (e.g. Cadence Sigrity/PowerSI, Ansys).
• Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and AutoCAD file exchange.
• Experience with package/IC co-design environments (e.g. Cadence Integrity 3D-IC).
• Scripting for design automation and rule checking.
• Experience at a startup or on a first-of-its-kind product, where the design rules did not exist yet.

Responsibilities

• Layout execution: Deliver RDL/UBM and package substrate layouts for optical engine products and test vehicles, from floorplan through tape-out. Define and release bump maps, ball maps, and escape routing strategies for multi-die assemblies (PIC, EIC, and light source die). Design to 200G/lane-class electrical requirements, ensuring differential pair routing, reference-plane integrity, crosstalk isolation, and power delivery for high-current, low-noise rails.
• Co-design and floor planning: Participate from the concept phase, producing preliminary floorplans and stack-up proposals that balance electrical, optical, thermal, and mechanical constraints. Iterate with SI/PI engineers on test routes to converge routing topologies and design rules.
• Design rules, DFM, and supplier engagement: Work directly with wafer fabs, substrate suppliers, and OSATs to capture and negotiate design rules, stack-ups, and assembly constraints. Generate fab and assembly release packages; drive DFM/DFA closure and design reviews through to sign-off. Flag rule conflicts early and propose alternatives.
• Verification and automation: Run and own physical verification, including DRC, connectivity/LVS-style netlist checks, and cross-domain consistency between die, package, substrate, and board. Manage netlists for heterogeneous assemblies across revisions and product variants. Build scripted automation (SKILL, Python, or equivalent) for repetitive layout, checking, and release tasks.
• Build support: Support test vehicle definition, first builds, bring-up, failure analysis, and yield learning, including layout changes driven by assembly reality.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree