Senior ML Compiler Engineer

femtoAI•San Bruno, CA

12h

About The Position

You will design and build core components of our ML compiler, owning critical parts of the transformation and optimization pipeline. Your work will directly determine whether models fit within hardware constraints and achieve real-time performance.

Requirements

4+ years of experience in compilers, systems, or performance engineering
Masters or PhD in Computer Science, Electrical Engineering, Math, or a related field
Deep experience with at least one: ML compiler frameworks (MLIR, TVM, XLA, etc.), Low-level optimization (scheduling, memory, tiling)
Proven ability to design non-trivial compiler systems or passes
Strong intuition for performance across compute, memory, and data movement
Comfort working with hardware constraints

Nice To Haves

Experience with constraint solvers (MILP, ILP, CP)
Background in accelerator architectures or embedded systems
Experience optimizing ML workloads for latency/power
Familiarity with DSP or real-time signal processing

Responsibilities

Design and implement compiler architecture across: IR design and transformation pipelines, Optimization strategies for scheduling, tiling, and memory reuse
Lead development of complex compiler passes such as: Global memory allocation and liveness-driven reuse, Cross-operator fusion and graph partitioning, Hardware-aware scheduling strategies
Develop cost models and optimization heuristics
Explore advanced techniques: Constraint-based optimization (e.g., ILP/MILP/CP), Scheduling optimization
Drive debugging of system-level issues (correctness, performance, HW mismatches)
Collaborate with hardware teams on co-design of abstractions and execution models