Senior Mixed Signal IP Enablement and Debug Engineer

Intel•Folsom, CA

9d•$141,910 - $269,100•Hybrid

About The Position

Join Intel's Hard IP Development Group (HIPD) within the Central Engineering Organization, where innovation meets execution. Our team develops industry-leading intellectual property that powers high-performance products across Server, Client, and Networking SoCs, as well as solutions for Intel Foundry customers. HIPD creates a comprehensive portfolio of cutting-edge Mixed Signal IPs including PLLs, Serial and Parallel IO PHYs (DDR/LPDDR, PCIe, USB, Type-C, UCIe Die-to-Die), and Ethernet PHYs. As part of our IO Post Silicon Validation Debug team, you'll work with a dynamic group of engineers who serve as the critical bridge between IP design teams and SoC customers throughout the validation and debug process.

Requirements

Bachelors and 5+ years of experience or Masters degree and 3+ years of experience in Computer Engineering, Electrical Engineering, or in a related field.
Experience in IP Integration, pre-silicon verification, Electrical or Functional Post Silicon validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die).
2+ years of experience with the lab hardware and software.
Experience using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs (Bit Error Ratio Testers).
Experience with at least one or more industry standard IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet, etc.
Either PHY or Controller experience is good.
Able to work independently with design team and customers to solve issues either remotely or onsite.
Able to lead on IP debug as situation arises in addition to hands on debug.

Nice To Haves

Ph.D. degree in Computer Engineering, Electrical Engineering, or in a related field.
Experience in signal integrity, power delivery, IBIS-AMI model development and silicon co-relation.
Pre-silicon design or simulation experience in logic, circuits, firmware or MRC and mixed signal validation.

Responsibilities

Customer-Focused IP Enablement: Partner closely with SoC customers and IP design teams to deliver comprehensive pre-silicon to post-silicon IP Integration and Debug support.
Develop and execute test plans and content using AI-driven tools and Python/System Verilog scripting.
Conduct SoC board design reviews and provide technical recommendations.
Perform signal integrity and power integrity simulations to optimize design performance.
Silicon Validation & Debug Leadership: Serve as the IP team representative during SoC power-on activities for test chips and products.
Provide hands-on IP enabling support throughout the silicon bring-up process.
Lead identification, investigation, and resolution of IP-related silicon issues.
Execute timely debugging and disposition of customer issues and sightings.
Technical Problem Solving: Conduct both pre-silicon and post-silicon issue reproduction and analysis.
Drive root cause analysis initiatives with comprehensive failure analysis.
Collaborate across cross-functional teams to deliver robust solutions.
Maintain customer obsession by ensuring rapid resolution of IP-related challenges.