Senior Mask Design Engineer

Infineon•San Jose, CA

68d•Onsite

About The Position

As a Senior Mask Design Engineer in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Requirements

Candidates who have passion for layout design, eye for detail, drive for learning and applying best practices for analog layout.
Bachelor’s Degree in Engineering or Certificate program in Circuit Layout
Understand and have hands-on experience in analog layout from scratch,
Strong understanding of analog circuit layout concepts in submicron and Fin-FET CMOS technologies
Strong understanding on matching, parasitic reduction, ESD, DFM etc.
Good understanding of design rules and how to resolve violations
Good technical, analytical & problem-solving skills in analog layout
Ability to work as strong team player and participate in cross-functional activities
Clear verbal and written communication skill to exchange ideas with designers and strong initiative at work

Responsibilities

Perform layout design of critical custom analog circuits using state-of-the art tools (Cadence Virtuoso & Mentor Calibre) and Analog layout techniques
Work closely with analog circuit designers to iterate circuit layouts to achieve target performance
Perform verification of layout design against foundry design rules and resolve violations.
Participate in layout design of RF circuits (block/IP/chip) floor planning from scratch, performing routing & layout verification and resolve violations
Conduct thorough layout design reviews with circuit designers