Senior Manager, Test, Manufacturability, Reliability and Quality

NVIDIA•Santa Clara, CA

2d•$232,000 - $368,000

About The Position

NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Senior Manager to lead our Test, Manufacturability, Reliability & Quality (TMRQ) organization. This is not a coordination role. Your work decides if a product can be built at scale and trusted in the field. These include production test development (SLT, BLT), control run flow, system reliability stress (HTOL), platform- and board-level manufacturing issue closure, and field diagnostic test development. You lead a team of individual contributors and a first-line manager at the layer where silicon, platform, and software collide with manufacturing reality. Decisions you make show up in yield curves, production ramp, and customer escapes. You are the leader the program turns to when a build is stuck, a control run is fallout-heavy, or a field return points back at silicon. The exceptional hire also uses AI deliberately — with demonstrated workflow impact and the judgment to know where it compresses real work and where it introduces risk.

Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Systems Engineering, or related field (or equivalent experience).
12+ years in production test, system validation, post-silicon integration, or reliability engineering in a high-volume silicon environment, including 5+ years in management.
Strong EE fundamentals across DFT, BIST, digital design, computer architecture, fault models and fault analysis, power and timing analysis, sampling, and statistics.
Hands-on expertise across the production test stack (ATE, SLT, BLT), Control Run methodology, FinFET-class manufacturing processes, and PVT/binning dependencies.

Nice To Haves

Background in GPU, CPU, AI accelerator, or other large-SoC programs — you know how complexity at scale changes the failure landscape.
Applied AI tools in production test or debug workflows — faster analysis, smarter triage, automated reporting — and can describe the outcome and the guardrails you put in place.
Track record of building and retaining senior technical talent in a highly matrixed organization, including guiding first-line managers to become autonomous leaders.
Ability to operate independently on hard, ambiguous problems—and collaborate clearly across functions.

Responsibilities

Keep programs moving. Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack CR, and system reliability stress (HTOL) across every GPU, SoC, and CPU silicon program.
Close the hardest multi-functional failures. Resolve Vmin and binning escapes, performance shortfalls, and power anomalies by driving root-cause across design, methodology, DFT, ATE, package, software/firmware, and manufacturing — and own the WARs and productized fixes through to confirmation.
Give leadership the clarity to act. Convert raw integration signals — CR fallout, BLT/SLT yield, SHTOL/CHTOL data, RMA trends, customer escalations — into decision-ready options that enable executive leadership to act with confidence on POR, QS/PS gates, and ramp-impacting risks.
Raise the execution bar across every program. Establish operational objectives, and refine closed-loop methodologies that improve cycle time, first-pass yield, test-time reduction, escape rate, and DPPM.
Prevent field escapes from recurring. Take ownership of manufacturing issues at both platform and board levels. Conduct root-cause analysis on returns and field escapes. Use field signals to develop screening, process, and build changes that improve quality.
Build the team the organization depends on. Hire, develop, and retain your manager and lead engineers across multiple geographies — grow ICs into recognized subsystem experts and develop your first-line managers into independently operating leaders.