Senior Manager, ASIC Design Engineering

Cornelis Networks, Inc.•San Jose, CA

2d•Remote

About The Position

At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. Cornelis Networks is looking for a Senior ASIC Design Engineering Manager to lead and grow our RTL design engineering team. Reporting to the VP of ASIC Engineering, with direct exposure to executive leadership, this leader will manage a team of talented design engineers and drive full-lifecycle development of Cornelis’ next-generation, high-performance networking ASICs. The role is accountable for building and driving RTL implementation schedules across all SoC subsystems and full-chip milestones. Success requires deep hands-on expertise in advanced RTL design implementation, methodologies, and SoC flows, from microarchitecture definition through RTL delivery, tape-out readiness, and cross-functional execution with Architecture, Design Verification, Emulation, and Physical Design. This leader will also own headcount planning, hiring, and organizational strategy to build a nimble, efficient, world-class design team. Exposure to AI-based design flows and methodology is preferred. This role is intended for a senior engineering leader who can combine hands-on ASIC RTL design expertise with disciplined program execution, cross-functional coordination, and team building at scale.

Requirements

15+ years in the semiconductor industry, preferably in high performance designs on advanced technology nodes, with at least 5 years in people management
B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience
Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams. You must know "how the work gets done" to manage the people doing it.
Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment. Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies.
Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink.
Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).

Nice To Haves

Exposure to AI based design implementation and verification flows, scripting for automation, milestone tracking and flow integration
Experience building globally distributed ASIC design teams and scaling engineering practices in a remote environment.

Responsibilities

Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans.
Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track.
Align RTL delivery schedules with DV and emulation enablement and manage feedback loops and dependencies efficiently.
Facilitate physical design handoffs by ensuring design teams provide high-quality RTL and constraints that minimize timing-closure iterations.
Track physical design feedback and delivery schedules to support physical design signoff and tape-out milestones.
Lead long-term headcount planning and organizational design for the ASIC department.
Identify skill gaps and execute global talent acquisition strategies that support the product roadmap.