Senior Manager, ASIC Chip Engineering

NVIDIA•Us, CA

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work, to amplify human imagination and intelligence. We are seeking an ASIC Chip Manager to help drive development of future SoC processors to be used in client, workstation, embedded, and automotive markets. Make the choice to join our dynamic team today!

Requirements

BSEE (MSEE / MSCE preferred) or equivalent experience
Minimum of 10 overall years of proven experience in chip development, with at least 5+ years managing an SoC or a key sub-system.
Experience in development cycle of graphics processing, memory, and I/O sub-systems in SOC chips.
Deep knowledge of the entire chip life cycle phases from concept to production, including: Markets, competition, and architecture; Front-end flows including micro-architecture, low-power design, RTL coding, verification, and emulation; Back-end flows including physical design, clock/reset distribution, and DFT; Silicon bring-up, reliability, and qualifications
Ability to multi-task effectively across simultaneous projects and drive the resolution of complex technical issues in a highly matrixed engineering team.
Excellent written, verbal, and technical communications skills.

Nice To Haves

Strong algorithm development and programming skills
Good understanding of the client and automotive markets
Experience with safety standards such as ISO26262 and delivering safety hardware and software

Responsibilities

Driving the execution of SOCs from concept to production.
Define, and track project achievements and dependencies across multi-functional teams.
Coordinate the activities of IP design, integration, DFT, physical design, VLSI, emulation, software, and operation teams to ensure successful productization with the first silicon.
Identify and characterize key technical risks and work with engineering and management teams to identify mitigation strategies.
Work in a highly matrixed and efficient global engineering team.
Provide technical leadership to the team.
Present the progress of complex efforts across many teams using key performance indicators and identify risk areas and mitigation strategies.
Identify and implement key data analytics and automation flows using various programming languages that continuously improves the execution efficiency across the organizations.
Drive after action reviews to identify and deploy creative out-of-the-box solutions for continuous improvement of the project workflows and execution.