Senior LPU ASIC Engineer

NVIDIA•Us, CA

2d•Hybrid

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join NVIDIA and become part of a team advancing the frontiers of AI technology! As we lead innovation in AI and accelerated computing, we seek a Senior LPU ASIC Engineer to contribute to our outstanding progress in chip design. At NVIDIA, you’ll collaborate with extraordinary talent and thrive in an environment that values diversity, collaboration, and remarkable accomplishments.

Requirements

B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred) with 5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes.
Proven track record of driving designs through the complete RTL-to-GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification.
Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi-voltage domain architectures.
Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and sign-off timing analysis (MCMM STA) using complex constraints.
Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle.
Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure.
Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations.
Expert-level command of industry-standard tool suites for end-to-end physical design flows.
Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations for enhanced design efficiency.

Nice To Haves

Specialized experience in the physical design of blocks and partitions containing high-speed SerDes IPs, such as PCIe, CXL, C2C, and Die-to-Die interfaces a plus.

Responsibilities

Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC at the block/partition level and top level.
Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation.
Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout.
Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.