Senior ASIC CAD Engineer

Palo Alto Networks•Office - USA - CA - Headquarters, CA

3d•$173,600 - $280,700•Onsite

About The Position

Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. As an ASIC CAD Engineer you will be the critical bridge between frontend logic and physical design teams. Your primary mission is to take front-end SystemVerilog code and successfully execute Logic Synthesis, Static Timing Analysis (STA), Power Optimization, and formal constraint management. You will also leverage your strong scripting skills to maintain and automate the underlying infrastructure, flows, and compute environments required to keep this design pipeline running at maximum efficiency.

Requirements

BS/MS in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of experience in ASIC front-end design, synthesis, and timing closure.
Proven track record of delivering clean, verified netlists to foundries or external ASIC vendor layout teams.
Proven track record of integrating, and configuring design constraints for IP blocks for high-speed interfaces such as PCIe, Ethernet, or DDR.
Deep production experience running standard industry tools like Synopsys Design Compiler/PrimeTime or Cadence Genus/Tempus.
Expert-level scripting capabilities using Perl, Python, Tcl, and Linux Shell environments.

Responsibilities

Drive full-chip and block-level logic synthesis, achieving optimal Power, Performance, and Area (PPA) over advanced process nodes.
Formulate master timing constraints (SDC) and execute sign-off Static Timing Analysis (STA) to resolve setup, hold, and clocking violations.
Implement low-power implementation strategies using UPF power intent architectures and analyze dynamic gate-level power profiles.
Act as the definitive technical liaison to our external P&R ASIC vendor, compiling comprehensive design handoff packages and reviewing post-layout parasitic data to secure tape-out closure.
Develop and enhance Perl, Python and Tcl-based scripts to automate our core front-end implementation and validation flows.
Support the maintenance of our ASIC CAD infrastructure and design flows required to keep this design pipeline running at maximum efficiency.