Senior IO Validation Engineer

NVIDIA•Santa Clara, CA

13d•Hybrid

About The Position

NVIDIA's High-Speed Interconnect (HSIC) team is seeking a versatile engineer to be part of a Silicon Hardware team. You will dive into next-gen high speed interconnects like NVLink and NVLink-C2C to make advancements in efficiency and stability. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from artificial intelligence, consumer graphics, self-driving cars, and more.

Requirements

BS or MS degree in EE/CE or equivalent experience.
Effective in a collaborative environment.
8+ years working in HSIO development, bringup planning, HSIO functional and electrical validation, and/or power optimization.
Working experience in a few of the following areas: HSIOs like PCIE or chip-to-chip interconnects including understanding of process/temp/voltage sensitivity on BER.
Identifying full chip data paths for HSIO saturation and working with applications to stress test for stability, perf, and power.
System level and interconnect power management optimizations.
Experience with large scale Data Center topologies across hosts, switches, retimers and end points.
Understanding of firmware/driver structures and their interaction with HW.
Strong EE fundamentals, knowledgeable in computer architecture, high speed interfaces, timing analysis, process variations, statistical error rates and power analysis.

Responsibilities

Contribute to design of next generation of high-speed IOs, including NVLink and NVLink-C2C.
Responsible for IO power optimizations and continuing to push energy efficiency.
Ensure interoperability with connected devices and system components in complex interconnect topologies.
Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams.
Work closely with other engineering teams such as system architects, mixed signal and design, DGX, software/firmware, HW/SW QA, operations and AE teams to drive design, development, debug and release of next generations products.