Senior High Speed Mixed-Signal I/O & Analog Layout Engineer

Saige Partners • San Jose, CA

3d • Remote

About The Position

We are seeking an experienced Senior High-Speed Mixed-Signal / Analog IC Layout Engineer to join our advanced silicon design team. In this role, you will collaborate closely with circuit designers based in San Jose, California, to develop and implement high-performance custom layouts for next-generation mixed-signal integrated circuits. You will be responsible for the physical layout of complex analog and high-speed circuits, including high-speed SERDES receivers (RX), transmitters (TX), PLLs, CDRs, voltage-controlled oscillators (VCOs), analog reference circuits, and other critical building blocks. This position requires a strong understanding of advanced CMOS technologies, layout optimization techniques, and industry-standard EDA tools to ensure designs meet performance, area, reliability, and manufacturability requirements.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline with 5+ years of professional IC layout experience; OR 8+ years of professional integrated circuit layout experience in lieu of a degree.
• Strong experience with custom analog and mixed-signal IC layout.
• Proficiency with Cadence Virtuoso and physical verification tools including Calibre LVS and DRC.
• Experience working with advanced sub-micron CMOS technologies.
• Strong understanding of layout matching techniques, parasitic optimization, reliability considerations, and design rule compliance.
• Excellent communication skills with the ability to collaborate effectively across geographically distributed engineering teams.
• Self-motivated with the ability to work independently while managing multiple priorities.

Nice To Haves

• Extensive experience designing high-speed SERDES layouts, including TX, RX, PLL, CDR, VCO, clocking circuits, and analog reference blocks.
• Experience with advanced semiconductor process nodes, including FinFET (14nm, 8nm, 4nm) and Gate-All-Around (2nm) technologies.
• Experience designing layouts supporting data rates up to 224 Gb/s .
• Working knowledge of Linux development environments.
• Experience with Cadence SKILL or SkillCAD automation.
• Familiarity with chip-level physical design including bump planning, pad ring implementation, and ESD strategies.
• Experience leading small layout teams and supporting successful analog or mixed-signal IC tape-outs.
• Strong technical documentation and written communication skills.

Responsibilities

• Partner with remote circuit designers to develop chip floorplans and optimize layouts for performance, area, parasitics, and manufacturability.
• Create custom analog and mixed-signal layouts for high-speed SERDES and related circuitry using Cadence Virtuoso.
• Optimize layouts to minimize parasitic effects while maximizing circuit performance and silicon efficiency.
• Develop project schedules, estimate layout effort, and execute work to meet aggressive development timelines.
• Interpret foundry process documentation and implement solutions to address design rule requirements, latch-up prevention, reliability concerns, and manufacturability.
• Perform layout verification and deliver DRC- and LVS-clean designs using industry-standard verification tools.
• Collaborate with cross-functional engineering teams to resolve design, verification, and implementation challenges.
• Contribute to chip-level physical design activities, including bump planning, pad ring development, ESD implementation, and tape-out preparation.
• Clearly communicate technical issues, layout trade-offs, and project status through meetings, documentation, and written communication.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior