Senior High-Speed IO Validation Engineer

NVIDIA•Santa Clara, CA

2d•$136,000 - $258,750•Onsite

About The Position

We are now looking for a Senior High-Speed IO (HSIO) Validation Engineer to join our hardware product team! This is an outstanding opportunity to work with next-generation GPU, CPU and high-performance computing platforms, driving system-level debug from bring-up all the way to full-scale production. Join a team that pushes technical boundaries, fosters close collaboration, and holds a high bar for quality!

Requirements

BS+ in EE/CE or equivalent experience.
3+ years of post-silicon HSIO validation or system bring-up experience.
Ability to work on site in a hardware lab environment 5 days a week at NVIDIA HQ.
Solid understanding of at least one high-speed interface protocol — PCIe, NVLink, C2C, Ethernet, USB, CXL, Display and/or SerDes/signal integrity at the PHY level, including link training and system-level operation.
Hands-on experience with lab equipment such as high-bandwidth DSOs, BERTs, protocol/logic analyzers, protocol exercisers, and TDR.
Proven system-level debug skills on complex hardware platforms.
Strong verbal and written communication skills, with the ability to collaborate across teams and suppliers to deliver quality products on tight schedules.

Nice To Haves

Proven experience debugging PCIe physical and link layer behavior, including link training, equalization, and lane margining; solid understanding of the data link and transaction layers.
Experience with NVLink, C2C, or other proprietary chip-to-chip interconnects.
Strong signal integrity background — SerDes equalization, eye/margin analysis, jitter decomposition, and channel modeling.
Experience with Ethernet (multi-Gbps to 400G+/800G) or Display Port/HDMI validation.
Experience with CXL — the CXL.io/.cache/.mem protocols and memory-coherency validation over the shared PCIe Gen5/6 PHY

Responsibilities

Own HSIO validation of NVIDIA products end-to-end, including test plan development, automation, design-for-validation requirements, resource planning, coverage metrics, test execution, bug resolution, and release to production.
Validate high-speed interfaces including PCIe, NVLink, C2C (Chip-to-Chip), Ethernet, USB, DP, HDMI, CXL etc. across the protocol, link, and physical layers.
Bring up new hardware platforms and debug sophisticated board- and system-level issues, working closely with logic/circuit design, board design, simulation, diagnostics, firmware, and software teams across multiple time zones.
Review board schematics, PCB layouts and BOM, provide development and component feedback, and ensure interoperability with connected devices in complex interconnect topologies.
Drive signal integrity characterization, link tuning, and margin analysis to ensure specification compliance, and efficient workload performance.
Define and drive HSIO functionality test coverage from link bring-up through stress and corner-case scenarios, including link training, error handling, power management, and interoperability across silicon and platform configurations.
Develop test automation to scale validation coverage and improve efficiency.
Provide engineering support to manufacturing during NPI and MP stage.