Senior Hardware Systems Engineer
About The Position
As an Senior Hardware Systems Engineer within EverPure’s EXA Hardware Engineering organization, you will serve as a primary technical authority driving the architectural vision, end-to-end design, and system-level validation of our next-generation enterprise and cloud-scale storage platforms. In this principal-level role, you will define the technology roadmap that bridges deep silicon/board-level hardware innovation with complex, multi-node cloud execution. You will establish design patterns, set high-speed and power/thermal benchmarks, and lead technical strategy across internal platform software teams, cross-functional executives, and global OEM/ODM/JDM partners. By defining next-generation server architectures, rack-scale power/thermal strategies, and zero-downtime resilience models, you will ensure EverPure maintains its industry-leading edge in storage performance and platform reliability.
Requirements
- Mastery of Enterprise Server & Storage Systems: Deep architectural expertise in high-density x86 enterprise server systems, rack-scale power delivery topologies (power-tree modeling, transient analysis), dynamic thermal management, high-performance storage protocols (NVMe-oF, CXL), and multi-node rack architectures.
- Deep Hands-On Bring-Up & Diagnostics: Extensive experience executing complex system bring-ups, high-speed signal integrity validation (PCIe Gen 5/6, high-frequency buses), and deep-dive hardware failure analysis using advanced lab instruments and telemetry architectures (BMC, Redfish, IPMI, PCIe analyzers, SMART logs).
- Validation Infrastructure & Automation Expertise: Proven success building scalable, programmatic validation pipelines (Python/Shell) and rigorous system stress testing methodologies to qualify enterprise-grade L10/L11 infrastructure.
- Rack-Scale & Network Integration Mastery: Demonstrated expertise in setting up, validating, and debugging rack-level interconnectivity spanning servers, high-speed switches, active optics, and fabric topologies. Familiarity with leaf-spine networks, RoCE, RDMA, InfiniBand, and BGP is highly desirable.
- MTS 5 Technical Leadership & Mentorship: Track record of acting as a technical lead and force multiplier across multi-disciplinary engineering organizations. Ability to translate broad business objectives into concrete technical roadmaps, mentor senior engineers, and influence vendor CTO/engineering organizations.
Nice To Haves
- Familiarity with leaf-spine networks, RoCE, RDMA, InfiniBand, and BGP is highly desirable.
Responsibilities
- Define and own the end-to-end multi-generational hardware roadmap for enterprise storage platforms.
- Drive architectural trade-off decisions across compute (x86/ARM), memory subsystems, DPUs, high-speed fabrics (PCIe Gen 5/6, CXL), and media technologies to maximize storage density, performance per watt, and TCO.
- Lead system-level HW design reviews (schematics, layout, power tree design, thermal topology) across global OEM/ODM/JDM partners.
- Establish technical standards, engineering requirements documents (ERDs), and design guidelines to ensure flawless vendor execution.
- Architect overall hardware quality frameworks, comprehensive validation strategies, and advanced diagnostic models spanning parametric, functional, electrical, and full-stack software/firmware integration.
- Establish automated telemetry, stress-testing paradigms (e.g., FIO, SPEC, custom IO engines), and gating criteria for tier-0 production releases.
- Serve as the final technical escalation point for complex, systemic hardware, signal integrity, and storage-node failures.
- Lead dynamic task forces across hardware, firmware, software, and silicon vendors to drive root-cause analysis (RCA) and long-term corrective action (CA) for high-impact edge cases.
- Drive the architecture and adoption of automated test frameworks (Python/Bash) for hardware validation, L10 device-level, and L11 rack-level platform stability, continuously raising the bar for test coverage and cycle time reduction.
- Partner closely with executive engineering leadership, software architects, platform design, and network infrastructure teams to ensure tight HW/FW/SW co-design.
- Champion systemic improvements in reliability, availability, and serviceability (RAS).
Benefits
- flexible time off
- wellness resources
- company-sponsored team events
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What This Job Offers
Job Type
Full-time
Career Level
Senior
