Senior Hardware Design Engineer, Devices - HP IQ

HP • San Francisco, CA

1d

About The Position

HP IQ is HP’s new AI innovation lab, combining startup agility with HP’s global scale to build intelligent technologies that redefine how the world works, creates, and collaborates. They are assembling a diverse, world-class team focused on creating an intelligent ecosystem across HP’s portfolio, developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless. The role focuses on the design and development of low-power electronic devices, involving detailed schematic execution, validation, and debugging under the technical direction of senior engineers. The ideal candidate will have strong circuit fundamentals, hands-on experience with schematic and layout tools, and a background working within well-defined engineering processes.

Requirements

• Bachelors or Masters of Science degree in Electrical Engineering, Computer Science, or Physics, or a related field; advanced degree preferred.
• 5+ years of professional experience in electrical engineering and system architecture.
• Strong understanding of circuit fundamentals, including low-power analog and high-speed signaling.
• Hands-on experience with Cadence schematic capture and PCB layout tools.
• Proven experience executing schematic design, validation, and debugging.
• Ability to work effectively under technical direction and within cross-functional team.

Nice To Haves

• Experience leading or contributing to low-power consumer or medical electronic systems from concept through production.
• Background at top-tier organizations with proven, mature hardware development practices.
• Experience with small, space-constrained devices and power-sensitive designs.
• Strong problem-solving skills with the ability to debug complex hardware issues efficiently.

Responsibilities

• Power architecture responsibility for a wearable device covering SoC states, sensor, audio, and memory architecture tradeoffs at board level.
• Battery, PCM, and charging profile definition and validation.
• Design power experiments, test plans, and measurement & telemetry mechanisms across firmware and hardware to optimize power and performance.
• Build and maintain system-level power models to model expected power consumption for user profiles.
• Map power models by subsystem, correlating modeled behavior with instrumented measurements.
• Define user profiles, power and sleep states, and low-power operating modes.
• Partner closely with product, hardware, firmware, manufacturing, and regression QA to drive alignment and execution toward power targets.

Benefits

• Health insurance
• Dental insurance
• Vision insurance
• Long term/short term disability insurance
• Employee assistance program
• Flexible spending account
• Life insurance
• Generous time off policies, including; 4-12 weeks fully paid parental leave based on tenure
• 11 paid holidays
• Additional flexible paid vacation and sick leave

What This Job Offers

• Job Type: Full-time
• Career Level: Senior