Senior FPGA Design Verification Engineer

Intuitive•Sunnyvale, CA

6d•$152,000 - $257,200•Onsite

About The Position

This role involves the verification of FPGAs on da Vinci systems to ensure RTL functional correctness. The process spans from test planning to verification closure using coverage metrics. The engineer will be responsible for hands-on testbench development using UVM, collaborating closely with the design team to review specifications and architecture, extract features, and define the verification plan and coverage model. Key tasks include writing constrained random stimulus, implementing functional cover groups, debugging failures, tracking bugs, and analyzing coverage for closure.

Requirements

Advanced knowledge of HVL methodology (UVM)
Expertise in HVL and HDL (SystemVerilog, Verilog)
Experience defining coverage space and writing coverage models
Team player with excellent communication skills and the desire to take on diverse challenges
Experience writing scripts in languages such as Perl/Python
Solid verification skills in problem solving, constrained random testing, and debugging

Nice To Haves

Experience with Emulation/FPGA prototyping and Formal is a plus
Experience with ML-assisted flows, and agentic-AI automation frameworks to accelerate coverage closure, improve debug efficiency, and enhance overall verification throughput

Responsibilities

Verification of FPGA’s on daVinci systems for RTL functional correctness
Starting from test-planning to closing verification using coverage metrics
Hands-on testbench development UVM
Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model
Write constrained random stimulus and Implement functional cover groups
Debugging failures, bug tracking, and analyze and close coverage