Senior Electrical Engineer - FPGA Verification

RTX•Tewksbury, MA

3d•Onsite

About The Position

Raytheon is seeking an experienced Senior level Electrical Engineer to verify FPGA based designs for control and/or signal processing radar applications. This position can be for the Tewksbury, MA location or the Marlborough, MA location. The Radar Digital Products (RDP) Department at Raytheon brings the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. We deliver solutions that help our nation and allies defend freedoms and deter aggression, creating a safer, more secure world. Join us and help shape the future of aerospace and defense.

Requirements

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 5 years of prior relevant experience
Digital design verification
Proficient in SystemVerilog for verification
Hands-on experience verifying designs using UVM-based testbenches.
Experience with industry-standard simulators (e.g., Questa, VCS, Xcelium)
U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
The ability to obtain and maintain a U.S. government issued security clearance is required.
Active and existing security clearance required after day 1

Nice To Haves

Experience designing FPGAs using VHDL/Verilog
Solid understanding of constrained-random verification and functional coverage methodology
Familiarity with AXI, PCIe, Ethernet, DDR protocols.
Experience with regression management and debug of complex, intermittent failures
Ability to develop and maintain verification plans tied to design specifications and coverage closure criteria
Experience with version control systems (e.g., Git, ClearCase, SVN) in a team-based development environment
Proficiency with Git. Branching strategies, pull requests, and collaborative workflows
Experience with UVMF (UVM Framework) for structured, reusable testbench development
Familiarity with Vivado and Quartus FPGA simulation flows
Experience with scripting languages (Python, Tcl, Perl) for test automation and tooling
Familiarity with SLURM workload manager for job scheduling and compute cluster resource management
Prior experience mentoring junior verification engineers
Existing DoD security clearance

Responsibilities

Own or contribute to the successful completion of FPGA-based designs, on time and on budget
Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage using UVM
Create complete documentation including verification plan and report
Demonstrate self-motivation, with little supervision required
Work cooperatively with systems, hardware, software engineers, and program management to ensure product success
Support internal and external technical reviews