Senior FPGA Compiler (Router) Engineer

Altera•Toronto, ON

2d•CA$144,600 - CA$209,300•Onsite

About The Position

Altera is seeking a Senior FPGA Compiler Engineer (Routing) to join our team! This role focuses on the development and optimization of FPGA routing algorithms within the compiler toolchain, directly impacting performance, power, and usability of next-generation FPGA devices. The ideal candidate brings strong expertise in EDA algorithms, graph-based optimization, and FPGA/ASIC design flows, along with a passion for solving complex problems at scale.

Requirements

9+ years of experience in FPGA/ASIC design tools, EDA, or related fields.
Strong background in algorithms and data structures (graph algorithms, optimization techniques).
Experience with FPGA or ASIC design flows (placement, routing, timing closure).
Proficiency in C/C++ and software development best practices.
Familiarity with Routing algorithms (e.g., maze routing, negotiated congestion).
Familiarity with Timing-driven design methodologies.
Familiarity with Physical design concepts.
Ability to analyze complex systems and develop scalable, high-performance solutions.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Strong communication, teamwork, and interpersonal skills are essential to effectively collaborate across cross-functional teams and drive successful outcomes.

Nice To Haves

Experience with commercial FPGA toolchains (e.g., Quartus, Vivado).
Knowledge of FPGA architectures and interconnect fabrics.
Familiarity with parallel/distributed computing for EDA workloads.
Experience with scripting (Python, Tcl) for tooling and automation.
Background in timing analysis or placement algorithms.

Responsibilities

Design, implement, and optimize FPGA routing algorithms to improve performance, routability, and timing closure.
Contribute to the FPGA compiler flow, including placement, routing, and timing-driven optimization.
Analyze and improve runtime, memory efficiency, and scalability of routing algorithms for large designs.
Work closely with architecture, synthesis, timing (STA), and hardware teams to align routing strategies with device capabilities.
Investigate routing congestion, timing violations, and design bottlenecks; develop solutions to improve convergence.
Integrate routing features into existing compiler infrastructure and ensure robustness across diverse customer use cases.