Senior FPGA Circuit Design Engineer

Altera•San Jose, CA

2d•$149,100 - $215,000•Onsite

About The Position

Altera is seeking a Senior FPGA Silicon Design Engineer to focus on the design and development of complex FPGA circuits, programmable logic, and IP for next-generation FPGA products. This role involves owning significant portions of FPGA architecture and implementation, including core fabric logic, interconnect and routing, clocking, configuration, configurable memory blocks, and Network-on-Chip (NoC) capabilities. The engineer will apply deep expertise in FPGA and/or ASIC design to micro-architect, design, simulate, and verify complex circuits and logic, optimizing for power, performance, area, timing, reliability, and yield. Responsibilities include developing models, specifications, and design collateral for integration into broader hardware and software deliverables. As a senior technical contributor, the role requires close collaboration with various engineering teams, driving complex technical assignments, influencing design decisions, mentoring engineers, and contributing to improved design methodologies and processes.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Math, or a related field and 8+ years of industry experience in FPGA or ASIC design.
8+ years of experience in FPGA circuit, IP, or RTL design, including development of complex digital logic, programmable logic, or silicon subsystems.
8+ years of experience in microarchitecture and logic design for complex digital systems, including experience with FPGA fabric, interconnects, routing, clocking, configuration, memory structures, processor subsystems, or Network-on-Chip (NoC) architectures.
8+ years of experience with hardware design and simulation methodologies, including schematic entry, RTL development, behavioral modeling, circuit simulation, functional verification, or related front-end design methodologies.
8+ years of experience using industry-standard FPGA or ASIC design tools and flows, including simulation, synthesis, static timing analysis (STA), linting, design-rule or electrical-rule checking, and power analysis.
8+ years of experience developing or analyzing timing, power, performance, area, reliability, or yield characteristics of FPGA or ASIC circuits and IP.
8+ years of experience developing design models, specifications, or technical collateral used to integrate FPGA circuits or IP into larger hardware and software systems.
8+ years of experience collaborating with cross-functional engineering teams, including microarchitecture, SoC/full-chip, IP, interconnect/fabric, RTL design, verification, physical design, and/or silicon validation teams.
8+ years of experience independently driving complex technical assignments, resolving design and integration issues, and influencing technical decisions across multiple engineering disciplines.

Nice To Haves

8+ years of experience specifically designing or implementing FPGA routing, interconnect, or programmable fabric architectures.
8+ years of experience with FPGA core fabric logic, configurable memory blocks, clocking architectures, configuration logic, or Network-on-Chip (NoC) architectures.
8+ years of experience developing FPGA circuit models, timing models, power models, behavioral models, electrical-rule checking methodologies, or other design collateral.
8+ years of experience contributing to FPGA or ASIC silicon development through design, verification, integration, tape-out, silicon bring-up, or post-silicon validation.
8+ years of experience working across hardware and software interfaces to enable integration of FPGA circuits and IP into larger SoC or system architectures.
Demonstrated experience mentoring engineers and providing technical leadership on complex FPGA circuit, IP, or architecture challenges.

Responsibilities

Design and develop complex FPGA circuits and IP, including FPGA core fabric logic, interconnect and routing, clocking, configuration, configurable memory blocks, and Network-on-Chip (NoC) architectures.
Lead microarchitecture definition and perform circuit and logic design for complex FPGA blocks and subsystems, making technical tradeoffs to optimize power, performance, area, timing, reliability, and yield.
Develop schematics, RTL implementations, behavioral models, and simulations to evaluate and validate new FPGA circuit architectures and capabilities.
Perform functional and reliability verification of FPGA circuits and IP, working closely with verification teams to identify, debug, and resolve complex design issues.
Develop and maintain design models and collateral required to integrate FPGA circuits and IP into hardware and software deliverables, including circuit integration specifications, behavioral models, electrical rule checkers, design intent, timing models, and power models.
Analyze design results and drive improvements to meet aggressive power, performance, area (PPA), timing, reliability, and yield objectives.
Work closely with microarchitecture, SoC/full-chip, IP fabric and interconnect, RTL design, verification, physical design, and other cross-functional teams to integrate FPGA circuits and IP into larger systems.
Drive technical resolution of complex design, integration, simulation, timing, and functional issues across multiple engineering disciplines.
Contribute to the development of new FPGA capabilities and improved programmable logic architectures that enable faster and more efficient integration of Altera FPGAs into larger systems.
Lead or contribute to design methodology and flow improvements that increase design quality, development efficiency, and scalability across FPGA product generations.
Provide technical guidance and mentorship to less-experienced engineers and serve as a technical resource for complex FPGA circuit and IP design challenges.
Support silicon bring-up and post-silicon debug as needed by investigating hardware issues, validating design functionality, and applying lessons learned to future FPGA designs.