Senior FPGA Architect (Compute Test, North Reading)

Teradyne•North Reading, MA

8d•$154,900 - $247,800•Hybrid

About The Position

Teradyne's Compute Test Division develops advanced test solutions for next-generation silicon, including high-performance SoCs and accelerators powering modern compute and AI systems. We are seeking a Senior FPGA Architect to architect and deliver high-performance FPGA-based solutions at the heart of our test platforms. This role works at the intersection of FPGA design, board-level hardware, and system architecture to solve complex challenges involving high-speed interfaces, large digital systems, tight timing margins, and system-level constraints. Based on site in North Reading, Massachusetts, the position is expected to work in the office three days per week and collaborate across functions to deliver robust, scalable solutions that directly affect the quality and performance of cutting-edge semiconductor devices.

Requirements

8+ years of hands-on experience in FPGA design and development.
Deep expertise in Verilog/SystemVerilog for design and debugging.
Proven experience with AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
Strong understanding of digital design fundamentals and the ability to interpret schematics.
Experience with high-speed interfaces such as PCIe, DDR, SerDes, or similar technologies, and with protocols such as AXI4, USB, I2C, and SPI.
Demonstrated ability to bring up and debug FPGA designs on hardware platforms.
Scripting proficiency in TCL and Python for automation and tooling, plus experience with version control systems and collaborative development workflows.
Strong system-level thinking, sound architectural judgment, and the ability to debug across FPGA, board, and software boundaries.
Excellent communication, collaboration, technical leadership, and mentoring skills in cross-functional environments.

Nice To Haves

Experience with SystemVerilog-based verification methodologies such as UVM
FPGA SoCs and embedded processor subsystems
ATE or measurement equipment design
Signal integrity, high-speed serial interfaces, and transceivers
DDR, HBM, and Flash memory technologies
AI tools for engineering design

Responsibilities

Lead FPGA design from architecture through implementation and bring-up, including requirements definition, trade-off analysis, timing closure, resource optimization, and performance tuning.
Develop high-performance FPGA solutions involving complex interfaces and subsystem integration, along with automation and debug tools using TCL and Python.
Collaborate with hardware, software, systems, and design verification teams to deliver cohesive system-level solutions and achieve appropriate simulation and test coverage.
Build and execute validation strategies, including lab bring-up, debug, and root cause analysis using JTAG and lab instrumentation.
Partner on PCB and system design decisions that affect FPGA performance and integration.
Mentor junior engineers and serve as the technical lead for FPGA project teams.