Senior Failure Analysis Engineer, Optical Fault Isolation

NVIDIA•Santa Clara, CA

34d•$144,000 - $264,500

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are seeking a highly skilled Senior Failure Analysis (FA) Engineer to drive die-level logic fault localization for our advanced semiconductor devices. You will work closely with our Design, Test, and DFT teams to identify root causes of silicon failures, accelerate yield improvements, and ensure the highest quality of our cutting-edge products.

Requirements

MS degree in Electrical Engineering, Materials Science, Physics, or a closely related field (or equivalent experience).
5+ years of direct, hands-on experience in semiconductor failure analysis, yield engineering, or product engineering.
Strong practical experience with the Advantest 93k test platform.
Good understanding of DFT basics and logic fault localization.
Expert level experience on LFI techniques (LVP, EMMI, SDL, OBIRCH, or other photon/laser-based techniques).
Excellent problem-solving abilities, strong technical communication skills, and a proven track record of driving complex issues to resolution.

Nice To Haves

Experience with Teradyne Ultraflex plus

Responsibilities

Perform complex, hands-on failure analysis and root cause identification using physical and electrical fault isolation methodologies.
Utilize the Advantest 93K platform to test & characterize DUT and setup required test-looping to enable LVP, SDL and other FA techniques.
Leverage knowledge of Design for Test (DFT) basics—including Scan, BIST, and boundary scan—to interpret test patterns and guide fault isolation strategies.
Analyze test results to distinguish between design, fab process, or tester-induced failures, delivering actionable corrective actions.
Collaborate with Product Engineering, Test Engineering, and Foundry Engineering teams to resolve yield, performance, and reliability issues.