Senior Engineer, GPU RTL Design - Pixel Pipe

Samsung Electronics•San Jose, CA

4d•$139,000 - $208,400•Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! As a Senior Engineer GPU RTL Design Engineer, you will contribute to the design and development of complex RTL blocks and subsystems for Samsung’s next-generation mobile GPU IPs, delivering high-quality, scalable implementations that power premium smartphones and adjacent consumer technologies. In this mid-to-senior individual contributor role, you will collaborate closely with hardware and software design teams and work across multiple GPU functional domains—including control, datapath, memory systems, and fixed-function logic, with a focus on pixel processing and graphics pipeline stages. You bring curiosity, RTL design knowledge, and microarchitectural understanding to support design decisions, resolve cross-block challenges, and ensure robust, production-ready GPU designs across multiple IP generations.

Requirements

2+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or a Master's degree.
2+ years of hands-on experience in semiconductor RTL design for complex SoC, CPU, or GPU architectures.
Hands-on experience in RTL design using Verilog/SystemVerilog, including microarchitecture development, integration, and debug.
Working knowledge of GPU or high-performance digital design concepts, including control logic, datapath design, memory systems, and fixed-function acceleration within graphics or pixel processing pipelines.
Working knowledge of interpreting architectural specifications and driving design tradeoffs across performance, power, and area (PPA).
Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and design quality checks.
Strong analytical, and problem-solving skills, with the ability to identify and propose data-driven solutions.
Excellent written and verbal communication skills for technical documentation.
Excellent collaboration skills, with the ability to navigate ambiguity a fast-paced, global team environment.

Responsibilities

Contribute to the microarchitecture definition and RTL implementation of complex GPU blocks and subsystems, translating architectural specifications into efficient, maintainable, and scalable hardware designs, including pixel pipeline and fixed-function graphics logic.
Support the RTL lifecycle, driving design from microarchitecture through RTL development, integration, debug, and simulation readiness while ensuring consistent execution across multiple functional areas and projects.
Support technical excellence by driving design quality and accuracy, developing clean, synthesizable RTL, and collaborating with verification teams to enable thorough validation, resolve functional issues, and ensure coverage, robustness, and sustainability across complex graphics processing flows.
Resolve functional design challenges, working with architecture, physical design, and system-level teams to address interface definition, timing, power, performance, and area tradeoffs early in the design cycle, with strong consideration for graphics performance and pixel throughput efficiency.
Take initiatives on moderate-to-complex projects and help advance best practices, methodologies by exploring emerging GPU technologies and RTL design methodologies.